Nonvolatile dynamic ram circuit

Claim 2

A memory cell comprising a first transistor having a first terminal coupled to an input/output line, a second terminal and a control terminal for coupling said first terminal to said second terminal responsive to control signals, a first storage capacitor coupled to said second terminal, a second storage capacitor, a second transistor, having a floating gate, coupled between said first and second capacitors in such manner that said second storage capacitor is coupled to said first storage capacitor depending upon the presence or absence of charge on said floating gate, and said memory cell storing information with only said first storage capacitor when said floating gate is charged and said memory cell storing information with both said first storage capacitor and said second storage capacitor when said floating gate is discharged.

Claim 3

The memory cell as in claim 1 wherein said first storage capacitor, said second storage capacitor and said floating gate transistor are connected in parallel.

Claim 4

A memory circuit capable of information storage in two modes comprising a plurality of memory cells, each cell having a storage capacitor formed of a fixed capacitance structure and a variable capacitance structure, said storage capacitor having a floating gate to vary the capacitance of said storage capacitor by isolating the variable capacitance structure from the fixed capacitance structure so as to operate in a low capacitor state or by coupling the variable capacitance structure with the fixed capacitance structure so as to operate in a high capacitor state and a transistor for selectively coupling said storage capacitor to a sense line responsive to a selection signal, said floating gate being charged to define the low capacitor state and being uncharged to define the high capacitor state, said floating layer having a double level construction so that it is closer in proximity to a first region than to a second region, and a sense amplifier connected to said sense line for determining the presence or absence of stored charges in said low capacitor state in a first mode, and for determining the presence or absence of stored charges in said high capacitor state in a second mode.

Claim 5

A memory circuit capable of information storage in two modes comprising a plurality of memory cells, each cell having a storage capacitor formed of a fixed capacitance structure and a variable capacitance structure, said storage capacitor having a floating gate to vary the capacitance of said storage capacitor by isolating the variable capacitance structure from the fixed capacitance structure so as to operate in a low capacitor state or by coupling the variable capacitance structure with the fixed capacitance structure so as to operate in a high capacitor state and a transistor for selectively coupling said storage capacitor to a sense line responsive to a selection signal, said floating gate being charged to define the low capacitor state and being uncharged to define the high capacitor state, said floating layer having a double level construction so that it is closer in proximity to a first region than to a second region, and a sense amplifier connected to said sense line for determining the presence or absence of stored charges in said low capacitor state in a first mode, and for determining the presence or absence of stored charges in said high capacitor state in a second mode.

Claim 6

The memory circuit as in claim 3 wherein said sense line is discharged before a selected memory cell is coupled to said sense line for said sense amplifier to perform said determining operation in said first mode and wherein said selected memory cell is coupled to said sense line as said sense line is discharged for said sense amplifier to perform said determining operation in said second mode.

Claim 7

The memory circuit as in claim 4 wherein each determining operation in said first and second modes is performed by a charge race between a discharged first sense line and related memory cell and a discharged second sense line and a reference memory cell, said sense amplifier going into a state indicative of the results of the charge race.

Claim 8

The memory circuit as in claim 5 wherein said reference memory cell comprises a first and second reference capacitors, and a first and second transistors, each transistor associated with one of said reference capacitors for selectively coupling said associated reference capacitor to said second sense line responsive to a mode selection signal, whereby, for a determining operation in said first mode, said first reference capacitor is selected for said charge race and, for a determining operation in said second mode, said second reference capacitor is selected for said charge race.

Claim 9

The memory circuit as in claim 6 wherein said first reference capacitor and said second sense line have a capacitance less than the capacitance of said selected memory cell and said first sense line.

Claim 10

The memory circuit as in claim 7 wherein the capacitance of said second reference capacitor and said second sense line is intermediate that of the capacitance of said selected memory cell having a floating gate charged and said first sense line, and the capacitance of said selected memory cell, having a floating gate uncharged and said first sense line.

Claim 11

The memory circuit as in claim 3 further comprising means coupled to said plurality of memory cells for charging and discharging the floating gate of a selected memory cell.

Claim 12

The memory circuit in claim 9 wherein each of said memory cells comprises first and second regions disposed in a spaced-apart relationship in a semiconductor substrate, a capacitor plate layer disposed over said substrate and above said first and second regions, a floating gate disposed between said first and second regions and intermediate said capacitor plate layer and said substrate, said floating gate layer being electrically isolated from said first and second regions and said capacitor plate layer, and said floating gate charging and discharging means operates by increasing a voltage difference between said capacitor plate layer and one of said first and second regions such that charges can move therebetween.

Claim 13

The memory circuit as in claim 3 wherein said sense line is discharged before a selected memory cell is coupled to said sense line for said sense amplifier to perform said determining operation in said first mode and wherein said selected memory cell is coupled to said sense line as said sense line is discharged for said sense amplifier to perform said determining operation in said second mode.

Claim 14

The memory circuit as in claim 11 wherein each determining operation in said first and second modes is performed by a charge race between a discharged first sense line and related memory cell and a discharged second sense line and a reference memory cell, said sense amplifier going into a state indicative of the results of the charge race.

Claim 15

A memory cell comprising: a storage capacitor having a fixed capacitance structure and a variable capacitance structure; said storage capacitor being formed of first and second regions disposed in a spaced-apart relationship in a semiconductor substrate, a plate layer disposed over said substrate and above said first and second regions, and a floating gate layer disposed between said first and second regions and intermediate said plate layer and said substrate, said floating gate layer being electrically isolated from said first and second regions and said plate layers; said floating gate layer varying the capacitance of said storage capacitor by isolating the variable capacitance structure from the fixed capacitance structure so as to operate in a low capacitance state or by coupling the variable capacitance structure with the fixed capacitance structure so as to operate in a high capacitance state, said floating gate being charged to define the low capacitance state and being uncharged to define the high capacitance state; said floating layer having a double level construction as that it is closer in proximity to said first region than to said second region; a transistor having a first terminal coupled to said storage capacitor, a second terminal coupled to an input/output line, and a control terminal for coupling said storage capacitor through said input/output line responsive to control signals; and said transistor being formed of third and fourth regions disposed in a spaced-apart relationship in said semiconductor substrate and a transfer gate layer disposed over said substrate and between said third and forth regions, said transfer gate layer being electrically isolated from said third and fourth regions.

Claim 16

A memory cell comprising: a storage capacitor having a fixed capacitance structure and a variable capacitance structure; said storage capacitor being formed of first and second regions disposed in a spaced-apart relationship in a semiconductor substrate, a plate layer disposed over said substrate and above said first and second regions, and a floating gate layer disposed between said first and second regions and intermediate said plate layer and said substrate, said floating gate layer being electrically isolated from said first and second regions and said plate layers; said floating gate layer varying the capacitance of said storage capacitor by isolating the variable capacitance structure from the fixed capacitance structure so as to operate in a low capacitance state or by coupling the variable capacitance structure with the fixed capacitance structure so as to operate in a high capacitance state, said floating gate being charged to define the low capacitance state and being uncharged to define the high capacitance state; said floating layer having a double level construction as that it is closer in proximity to said first region than to said second region; a transistor having a first terminal coupled to said storage capacitor, a second terminal coupled to an input/output line, and a control terminal for coupling said storage capacitor through said input/output line responsive to control signals; and said transistor being formed of third and fourth regions disposed in a spaced-apart relationship in said semiconductor substrate and a transfer gate layer disposed over said substrate and between said third and forth regions, said transfer gate layer being electrically isolated from said third and fourth regions.

Claim 17

A memory cell as in claim 13 wherein said semiconductor substrate is of one conductivity type and said first, second, third and fourth regions are of another conductivity type.

Claim 18

A memory cell as in claim 14 wherein said floating gate layer, said plate layer and said transfer gate layer comprise polysilicon.

Claim 19

A memory cell as in claim 15 wherein said third region is coupled to said input/output line and said fourth is coupled to first region.

Claim 20

A memory cell as in claim 16 wherein said fourth and first regions are contiguous.