US4654831A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed CMOS current sense amplifier
Assignee: Advanced Micro Devices Inc
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Filing: 1985-04-11
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Granted: 1987-03-31
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Expires: 2005-04-11
Abstract
Abstract A CMOS current sense amplifier circuit for providing a high speed of operation includes a sense amplifier, a dummy sense amplifier and an operational sense amplifier. A memory array is formed of a plurality of core transistors which are arranged in a plurality of rows of word lines and a plurality of columns of bit-lines. A dummy bit-line is formed of a plurality of core transistors which are arranged in parallel along the rows of word lines. A first pass transistor and a plurality of Y-pass transistors are coupled between the sense amplifier and the memory array. Second and third pass transistors are coupled between the dummy sense amplifier and the dummy bit-line. A plurality of N-channel MOS transistors are used to clamp all of the bit-lines in the array and dummy bit-line to a ground potential. The operational sense amplifier is responsive to the sense amplifier, dummy sense amplifier and the clamping transistors for generating an output signal which has a fast response time when making a low-to-high transition (that is when selecting an unprogrammed memory cell).
Inventors
- 👤 Bhimachar Venkatesh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:53
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C7/06; G11C7/062; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
358 words
A CMOS current sense amplifier circuit for providing a high speed of operation comprising: sense amplifier means for providing a first output; a memory array formed of a plurality of core transistors which are arranged in n rows of word lines and m columns of bit-lines; a first pass transistor and a plurality of Y-pass transistors coupled between the first output of said sense amplifier means and said memory array; said first pass transistor having its drain coupled to the first output of said sense amplifier means and its gate connected to a first control terminal for receiving a false clamp pulse signal; said plurality of Y-pass transistors having each of their drains connected together and to the source of said first pass transistor, the sources of said plurality of Y-pass transistors being connected to a corresponding one of the m columns of bit-lines; dummy sense amplifier means for providing a second output; a dummy bit-line formed of a plurality of core transistors which are arranged in parallel along the n rows of word lines; second and third pass transistors coupled between the second output of said dummy sense amplifier means and said dummy bit-line; said second pass transistor having its drain coupled to the second output of said dummy sense amplifier means and its gate connected to a second control terminal for receiving the false clamp pulse signal; said third pass transistor having its drain connected to the source of said second pass transistor, its gate connected to a supply potential, and its source connected to the dummy bit-line; clamping means coupled to said memory array and dummy bit-line for maintaining all of the bit-lines at a ground potential; said first pass transistor, second pass transistor and clamping means being responsive to the false and a true clamp pulse signals for permitting the quick discharging of the first output of said sense amplifier means and of the second output of said dummy sense amplifier means; and operational sense amplifier means responsive to said first and second outputs for generating a third output at an output terminal which has a fast response time when making a low-to-high transition.
Claim 2
Dependent Claim
358 words
A CMOS current sense amplifier circuit for providing a high speed of operation comprising: sense amplifier means for providing a first output; a memory array formed of a plurality of core transistors which are arranged in n rows of word lines and m columns of bit-lines; a first pass transistor and a plurality of Y-pass transistors coupled between the first output of said sense amplifier means and said memory array; said first pass transistor having its drain coupled to the first output of said sense amplifier means and its gate connected to a first control terminal for receiving a false clamp pulse signal; said plurality of Y-pass transistors having each of their drains connected together and to the source of said first pass transistor, the sources of said plurality of Y-pass transistors being connected to a corresponding one of the m columns of bit-lines; dummy sense amplifier means for providing a second output; a dummy bit-line formed of a plurality of core transistors which are arranged in parallel along the n rows of word lines; second and third pass transistors coupled between the second output of said dummy sense amplifier means and said dummy bit-line; said second pass transistor having its drain coupled to the second output of said dummy sense amplifier means and its gate connected to a second control terminal for receiving the false clamp pulse signal; said third pass transistor having its drain connected to the source of said second pass transistor, its gate connected to a supply potential, and its source connected to the dummy bit-line; clamping means coupled to said memory array and dummy bit-line for maintaining all of the bit-lines at a ground potential; said first pass transistor, second pass transistor and clamping means being responsive to the false and a true clamp pulse signals for permitting the quick discharging of the first output of said sense amplifier means and of the second output of said dummy sense amplifier means; and operational sense amplifier means responsive to said first and second outputs for generating a third output at an output terminal which has a fast response time when making a low-to-high transition.
Claim 3
Dependent Claim
36 words
A current sense amplifier circuit as claimed in claim 1, wherein said sense amplifier means comprises a pair of P-channel MOS transistors, a pair of N-channel MOS transistors, a first output transistor and a load transistor.
Claim 4
Dependent Claim
36 words
A current sense amplifier as claimed in claim 2, wherein said dummy sense amplifier means comprises a pair of P-channel MOS transistors, a pair of N-channel MOS transistors, a second output transistor, and a load transistor.
Claim 5
Dependent Claim
66 words
A current sense amplifier circuit as claimed in claim 3, wherein said clamping means comprises a plurality of N-channel MOS transistors, each transistor having its drain connected to a separate bit-line of the m columns in said memory array and to the dummy bit-line, its source connected to the ground potential and its gate connected to a control terminal for receiving the true clamp pulse signal.
Claim 6
Dependent Claim
36 words
A current sense amplifier as claimed in claim 4, wherein said operational sense amplifier means comprises a pair of current mirror transistors and a pair of load transistors, a current source, and an output buffer stage.
Claim 7
Dependent Claim
47 words
A current sense amplifier circuit as claimed in claim 2, further comprising a first capacitor coupled to the first output of said sense amplifier means which is quicky discharged so as to facilitate the fast low-to-high transition at the third output of said operational sense amplifier means.
Claim 8
Dependent Claim
47 words
A current sense amplifier circuit as claimed in claim 6, further comprising a second capacitor coupled to said clamping means which is quicky charged up from the ground potential so as to facilitate the fast low-to-high transition at the third output of said operational sense amplifier means.
Claim 9
Dependent Claim
201 words
A high speed CMOS current sense amplifier circuit comprising: means for generating a sense amplifier output; means for generating a dummy sense amplifier output; means responsive to said sense amplifier output and dummy sense amplifier output for generating a differential sense amplifier output; array means formed of a plurality of core transistors which are arranged in a plurality of rows and columns, each column of said core transistors being connected to bit-lines, said array means being operatively connected to said amplifier sense output and said dummy sense amplifier output; clamping means connected to all of the bit-lines of said array means for clamping said bit-lines to a ground potential so that all bit-lines are required to charge up from the ground level; said clamping means including a plurality of N-channel MOS transistors, each transistor having its drain connected to one bit-line of the plurality of columns in said array means, its source connected to the ground potential and its gate connected to a control terminal for receiving a true clamp pulse signal; and output means coupled to said differential sense amplifier output and being responsive to said clamping means for generating an output signal which has a fast low-to-high transition time.
Claim 10
Dependent Claim
201 words
A high speed CMOS current sense amplifier circuit comprising: means for generating a sense amplifier output; means for generating a dummy sense amplifier output; means responsive to said sense amplifier output and dummy sense amplifier output for generating a differential sense amplifier output; array means formed of a plurality of core transistors which are arranged in a plurality of rows and columns, each column of said core transistors being connected to bit-lines, said array means being operatively connected to said amplifier sense output and said dummy sense amplifier output; clamping means connected to all of the bit-lines of said array means for clamping said bit-lines to a ground potential so that all bit-lines are required to charge up from the ground level; said clamping means including a plurality of N-channel MOS transistors, each transistor having its drain connected to one bit-line of the plurality of columns in said array means, its source connected to the ground potential and its gate connected to a control terminal for receiving a true clamp pulse signal; and output means coupled to said differential sense amplifier output and being responsive to said clamping means for generating an output signal which has a fast low-to-high transition time.
Claim 11
Dependent Claim
40 words
A current sense amplifier circuit as claimed in claim 8, wherein said means for generating the sense amplifier output comprises a pair of P-channel MOS transistors, a pair of N-channel MOS transistors, a load transistor, and a first output transistor.
Claim 12
Dependent Claim
41 words
A current sense amplifier circuit as claimed in claim 8, wherein said means for generating the dummy sense amplifier output comprises a pair of P-channel MOS transistors, a pair of N-channel MOS transistors, a load transistor, and a second output transistor.
Claim 13
Dependent Claim
32 words
A current sense amplifier circuit as claimed in claim 8, wherein said differential sense amplifier means comprises a pair of current mirror transistors, a pair of load transistors and a current source.
Claim 14
Dependent Claim
36 words
A current sense amplifier circuit as claimed in claim 8, further comprising a capacitor coupled to the sense amplifier output which is quickly discharged so as to facilitate the fast low-to-high transition of the output signal.
Claim 15
Dependent Claim
41 words
A current sense amplifier circuit as claimed in claim 12, further comprising a second capacitor coupled to the clamping means which is quickly charged up from the ground potential so as to facilitate the fast low-to-high transition of the output signal.
Claim 16
Dependent Claim
167 words
A high speed CMOS current sense amplifier circuit comprising: differential sense amplifier means for generating an output signal; array means formed of a plurality of core transistors which are arranged in a plurality of rows and columns, each column of said core transistors being connected to bit-lines; means for connecting said array means to said differential sense amplifier means; clamping means connected to all of the bit-lines in said array means for clamping said bit-lines to a ground potential so that all bit-lines are required to charge up from the ground level; said clamping means including a plurality of N-channel MOS transistors, each transistor having its drain connected to one bit-line of the plurality of columns in said array means, its source connected to the ground potential and its gate connected to a control terminal for receiving a true clamp pulse signal; and said differential sense amplifier means being responsive to said clamping means so that the output signal has a fast low to high transition time.
Claim 17
Dependent Claim
167 words
A high speed CMOS current sense amplifier circuit comprising: differential sense amplifier means for generating an output signal; array means formed of a plurality of core transistors which are arranged in a plurality of rows and columns, each column of said core transistors being connected to bit-lines; means for connecting said array means to said differential sense amplifier means; clamping means connected to all of the bit-lines in said array means for clamping said bit-lines to a ground potential so that all bit-lines are required to charge up from the ground level; said clamping means including a plurality of N-channel MOS transistors, each transistor having its drain connected to one bit-line of the plurality of columns in said array means, its source connected to the ground potential and its gate connected to a control terminal for receiving a true clamp pulse signal; and said differential sense amplifier means being responsive to said clamping means so that the output signal has a fast low to high transition time.
Claim 18
Dependent Claim
32 words
A current sense amplifier circuit as claimed in claim 14, wherein said differential sense amplifier means comprises a pair of current mirror transistors, a pair of load transistors and a current source.
Claim 19
Dependent Claim
27 words
A current sense amplifier circuit as claimed in claim 14, wherein said connecting means includes first, second and third pass transistors and a plurality of Y-pass transistors.
References Cited (Backward Citations)
US4223394A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-30 | 1990-09-29 | 1991-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-30 | 1994-09-29 | 1995-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-30 | 1998-09-29 | 1999-03-31 | $7700.00 | Window Closed / Lapsed |