Electrically alterable, nonvolatile, floating gate type memory device with reduced tunnelling area and fabrication thereof

Claim 1

An electrically alterable, nonvolatile, floating gate type memory device, comprising a chip of semi­conductor material having a channel region of a first type of conductivity between a first and a second region of a second type of conductivity, formed at the surface of said semiconductor chip, said channel region providing a region within the semiconductor capable of passing an electric current between said first and said second region, a first level of conducting material, constituting said floating gate, extending over said channel region, substantially between said first and said second region and electrically insulated by means of a layer of dielectric material from said semiconducting material and from a second level of conducting material, constituting a control gate, overlying said first level of conducting material, characterized by the fact that, an appendix of conducting material, insulated from the underlying semiconducting material by a layer of tunnel oxide, essentially thinner than said layer of dielectric material, is formed at least along a length of an edge of said first level of conducting material adjacent to one of said first and second region by means of a self­aligned process and said appendix is electrically connected to said first level of conducting material forming said floating gate.

Claim 12

A method for forming a floating gate type, semicon­ductor memory device comprising a channel region between a drain region and a source region, and a floating gate of polycrystalline silicon superimposed to said channel region and insulated from the channel region by a dielectric layer of gate oxide and extending over said drain region at least in correspondence of a tunnelling area, in correspondence of which, the insulation between said floating gate and said drain region being constituted by a dielectric layer of tunnel oxide which is essentially thinner than said gate oxide, characterized by comprising the following steps: a) forming a layer of gate oxide; b) forming and defining a first level layer of poly­crystalline silicon above said channel region; c) masking and removing said gate oxide in correpon­dence of an area comprising at least a length of an edge of said first level of polycrystalline silicon, substantially coinciding with the geometric projec­tion of a boundary of said drain region; d) forming a layer of tunnel oxide; e) depositing a first matrix layer of polycrystalline silicon; f) masking and removing said first matrix layer of poly­crystalline silicon and said layer of tunnel oxide over an area comprising at least a portion of said edge of said first level of polycrystalline silicon noncoinciding with the said geometric projection of a boundary of said drain region; g) depositing a second matrix layer of polycrystalline silicon; h) anisotropically attacking said matrix layers of poly­crystalline silicon leaving a residual appendix of polycrystalline silicon belonging to said matrix layers along the edge of said first level of poly­crystalline silicon and electrically connected to said first level of polycrystalline silicon; i) removing said layer of gate oxide from the areas not covered by said first level of polycrystalline silicon and by said appendix; l) forming a new dielectric layer of gate oxide; m) forming an insulating dielectric layer over the top surface and over the lateral surface of said first level of polycrystalline silicon and of said appendix; and n) forming a second level of polycrystalline silicon above said first level of polycrystalline silicon, electrically insulated from the latter.

Claim 13

A method for forming a floating gate type, semicon­ductor memory device comprising a channel region between a drain region and a source region, and a floating gate of polycrystalline silicon superimposed to said channel region and insulated from the channel region by a dielectric layer of gate oxide and extending over said drain region at least in correspondence of a tunnelling area, in correspondence of which, the insulation between said floating gate and said drain region being constituted by a dielectric layer of tunnel oxide which is essentially thinner than said gate oxide, characterized by comprising the following steps: a) forming a layer of gate oxide; b) forming and defining a first level layer of poly­crystalline silicon above said channel region; c) masking and removing said gate oxide in correpon­dence of an area comprising at least a length of an edge of said first level of polycrystalline silicon, substantially coinciding with the geometric projec­tion of a boundary of said drain region; d) forming a layer of tunnel oxide; e) depositing a first matrix layer of polycrystalline silicon; f) masking and removing said first matrix layer of poly­crystalline silicon and said layer of tunnel oxide over an area comprising at least a portion of said edge of said first level of polycrystalline silicon noncoinciding with the said geometric projection of a boundary of said drain region; g) depositing a second matrix layer of polycrystalline silicon; h) anisotropically attacking said matrix layers of poly­crystalline silicon leaving a residual appendix of polycrystalline silicon belonging to said matrix layers along the edge of said first level of poly­crystalline silicon and electrically connected to said first level of polycrystalline silicon; i) removing said layer of gate oxide from the areas not covered by said first level of polycrystalline silicon and by said appendix; l) forming a new dielectric layer of gate oxide; m) forming an insulating dielectric layer over the top surface and over the lateral surface of said first level of polycrystalline silicon and of said appendix; and n) forming a second level of polycrystalline silicon above said first level of polycrystalline silicon, electrically insulated from the latter.