EEPROM memory system having selectable programming voltage for low power readability

Claim 2

A memory system comprising: voltage means for generating write and read voltages and selectively generating a programming voltage; a plurality of memory cells; and decoder means coupled to the voltage means for receiving the write, read, and programming voltages, and uniquely coupled to each of the memory cells for reading the cells by applying the read voltage to the cells during a read mode, and for writing the cells by applying the write voltage and the programming voltage to the cells during a write mode, the decoder means enabling the voltage means so that the programming voltage is generated from the write voltage during the write mode and disabling the voltage means so that the programming voltage is not generated during the read mode.

Claim 3

A memory system comprising: voltage means for generating programming voltages; row decoder means coupled to said voltage means for selectively supplying first, second, third and programming voltages; column decoder means coupled to said voltage means for selectively providing said third and programming voltages; and a plurality of memory cells each uniquely coupled between said row decoder means and said column decoder means, each of said cells comprising: a data terminal for receiving and transmitting data; a read enable terminal for receiving one of said first, second, and third voltages; a write/erase terminal for receiving one of said programming voltage and said third voltage; a program enable terminal for receiving one of said programming voltage and said third voltage; a current drain terminal; a first field effect transistor having its drain-source current path coupled between said data terminal and a node, and a gate coupled to said write/erase terminal; a second field effect transistor having its drain-source current path coupled between said data terminal and said node, and a gate coupled to said read enable terminal; and a floating gate field effect transistor having its drain-source current path coupled between said node and said current drain terminal, and a gate coupled to said program enable terminal; data being written into said cell when said programming voltage is applied from said row decoder to said write/erase terminal and to said data terminal, and the second voltage is applied from said row decoder to said read enable terminals and said third voltage is applied from said column decoder to said program enable terminal; data being read from said cell when one of (a) said first voltage is applied by said row decoder to said read enable terminal and said third voltage is applied by said column decoder to said write/enable terminal, said program enable terminal, and said current drain terminal and (b) said second voltage is applied by said row decoder to said read enable terminal and said third voltage is applied by said column decoder to said current drain terminal, said write/erase terminal, and said program enable terminal; said voltage means not generating programming voltages when data is being read; and data being erased from said cell when said programming voltage is applied from said row decoder to said write/erase terminal and said program enable terminal and said third voltage is applied by said column decoder to said data terminal and said current drain terminal, and said second voltage is applied from said row decoder to said read enable terminal.

Claim 4

A memory system comprising: voltage means for generating programming voltages; row decoder means coupled to said voltage means for selectively supplying first, second, third and programming voltages; column decoder means coupled to said voltage means for selectively providing said third and programming voltages; and a plurality of memory cells each uniquely coupled between said row decoder means and said column decoder means, each of said cells comprising: a data terminal for receiving and transmitting data; a read enable terminal for receiving one of said first, second, and third voltages; a write/erase terminal for receiving one of said programming voltage and said third voltage; a program enable terminal for receiving one of said programming voltage and said third voltage; a current drain terminal; a first field effect transistor having its drain-source current path coupled between said data terminal and a node, and a gate coupled to said write/erase terminal; a second field effect transistor having its drain-source current path coupled between said data terminal and said node, and a gate coupled to said read enable terminal; and a floating gate field effect transistor having its drain-source current path coupled between said node and said current drain terminal, and a gate coupled to said program enable terminal; data being written into said cell when said programming voltage is applied from said row decoder to said write/erase terminal and to said data terminal, and the second voltage is applied from said row decoder to said read enable terminals and said third voltage is applied from said column decoder to said program enable terminal; data being read from said cell when one of (a) said first voltage is applied by said row decoder to said read enable terminal and said third voltage is applied by said column decoder to said write/enable terminal, said program enable terminal, and said current drain terminal and (b) said second voltage is applied by said row decoder to said read enable terminal and said third voltage is applied by said column decoder to said current drain terminal, said write/erase terminal, and said program enable terminal; said voltage means not generating programming voltages when data is being read; and data being erased from said cell when said programming voltage is applied from said row decoder to said write/erase terminal and said program enable terminal and said third voltage is applied by said column decoder to said data terminal and said current drain terminal, and said second voltage is applied from said row decoder to said read enable terminal.

Claim 5

The memory system according to claim 2 wherein said first voltage, second voltage, and programming voltage have magnitudes greater than said third voltage.

Claim 6

The memory system according to claim 2 wherein said programming voltage has a magnitude substantially greater than said first voltage, second voltage, and third voltage, and said programming voltage is generated by multiplying said first voltage.

Claim 7

The memory system according to claim 2 wherein said first voltage has a magnitude greater than said second voltage.

Claim 8

The memory system according to claim 2 wherein said programming, first, second, and third voltages have decreasing magnitudes, respectively.

Claim 9

An electrically erasable programmable memory cell comprising: a data terminal for receiving and transmitting data; a read enable terminal for receiving one of a first, second, and third voltages; a write/erase terminal for receiving one of a programming voltage and a third voltage; a program enable terminal for receiving one of a programming voltage and a third voltage; a current drain terminal; a first field effect transistor having its drain-source current path coupled between said data terminal and a node, and a gate coupled to said write/erase terminal; a second field effect transistor having its drain-source current path coupled between said data terminal and said node, and a gate coupled to said read enable terminal; and a floating gate field effect transistor having its drain-source current path coupled between said node and said current drain terminal, and a gate coupled to said program enable terminal, whereby data from said data terminal is written into said cell when the programming voltage is applied to said write/erase terminal and said third voltage is applied to said read enable and program enable terminals, data is read from said data terminal when said first voltage is applied to said read enable terminal and said third voltage is applied to said write/erase, program enable, and current drain terminals, data is read from said data terminal when said second voltage is applied to said read enable terminal and said third voltage is applied to said write/erase, program enable, and current drain terminals, and data is erased from said cell when said programming voltage is applied to said write/erase and program enable terminals and said third voltage is applied to said read enable, data, and current drain terminals.

Claim 10

An electrically erasable programmable memory cell comprising: a data terminal for receiving and transmitting data; a read enable terminal for receiving one of a first, second, and third voltages; a write/erase terminal for receiving one of a programming voltage and a third voltage; a program enable terminal for receiving one of a programming voltage and a third voltage; a current drain terminal; a first field effect transistor having its drain-source current path coupled between said data terminal and a node, and a gate coupled to said write/erase terminal; a second field effect transistor having its drain-source current path coupled between said data terminal and said node, and a gate coupled to said read enable terminal; and a floating gate field effect transistor having its drain-source current path coupled between said node and said current drain terminal, and a gate coupled to said program enable terminal, whereby data from said data terminal is written into said cell when the programming voltage is applied to said write/erase terminal and said third voltage is applied to said read enable and program enable terminals, data is read from said data terminal when said first voltage is applied to said read enable terminal and said third voltage is applied to said write/erase, program enable, and current drain terminals, data is read from said data terminal when said second voltage is applied to said read enable terminal and said third voltage is applied to said write/erase, program enable, and current drain terminals, and data is erased from said cell when said programming voltage is applied to said write/erase and program enable terminals and said third voltage is applied to said read enable, data, and current drain terminals.

Claim 11

The memory system according to claim 7 wherein said first voltage, second voltage, and programming voltage have magnitudes greater than said third voltage.

Claim 12

The memory system according to claim 7 wherein said programming voltage has a magnitude substantially greater than said first voltage, second voltage, and third voltage, and said programming voltage is generated by multiplying said first voltage.

Claim 13

The memory system according to claim 7 wherein said first voltage has a magnitude greater than said second voltage.