Non-volatile memory cell having lightly-doped source region

Claim 2

A non-volatile memory cell structure comprising: heavily n-doped source and drain regions formed in the surface of a semiconductor substrate and separated by a p-doped channel region; a floating gate formed over and insulated from said channel region; a control gate formed over and insulated from said floating gate; a lightly doped region formed in said channel region beneath said floating gate and adjoining said source region, said lightly doped region spaced from the surface of said substrate.

Claim 3

The structure of claim 1 wherein said source and drain regions and said lightly doped region are n-doped silicon and said channel region is p-doped silicon.

Claim 4

The structure of claim 2 wherein said source and drain regions are doped with arsenic.

Claim 5

The structure of claim 2 wherein said source and drain regions are doped with phosphorus.

Claim 6

The structure of claim 1 wherein said lightly doped region is doped to between about 10 13 and 10 14 cm -2 .

Claim 7

The structure of claim 1 wherein said lightly doped region is doped with arsenic and/or phosphorous.

Claim 8

The structure of claim 1 wherein said cell is one cell is an array of cells.

Claim 9

The structure of claim 1 and further comprising a pocket region of conductivity type opposite that of said source and drain regions, said pocket region formed between said source region and said channel region.

Claim 10

The structured of claim 1 wherein said non-volatile memory cell comprises a flash EPROM cell.

Claim 11

The structure of claim 1 wherein said non-volatile memory cell comprises a UV erasable EPROM cell.

Claim 12

A non-volatile memory cell structure comprising: a first and second source/drain regions of a first conductivity type formed in the surface of a semiconductor substrate and separated by a channel region; a floating gate formed over and insulated from said channel region; a control gate formed over and insulated from said floating gate; a lightly doped region of said first conductivity type formed in said channel region beneath said floating gate and adjoining said first source/drain region, said lightly doped region spaced from the surface of said substrate.

Claim 13

A non-volatile memory cell structure comprising: a first and second source/drain regions of a first conductivity type formed in the surface of a semiconductor substrate and separated by a channel region; a floating gate formed over and insulated from said channel region; a control gate formed over and insulated from said floating gate; a lightly doped region of said first conductivity type formed in said channel region beneath said floating gate and adjoining said first source/drain region, said lightly doped region spaced from the surface of said substrate.

Claim 14

The structure of claim 11 and further comprising a pocket region of said second conductivity, said pocket region formed between said first source/drain region and said channel region.

Claim 15

The structure of claim 11 wherein said non-volatile memory cell comprises a flash EPROM cell.

Claim 16

The structure of claim 11 wherein said non-volatile memory cell comprises a UV erasable EPROM cell.

Claim 17

A non-volatile memory cell structure comprising: first and second source/drain regions of a first conductivity type formed in the surface of a semiconductor substrate and separated by a channel region of a second conductivity type which is different than said first conductivity type; a floating gate formed over and insulated from said channel region; a control gate formed over and insulated from said floating gate; a lightly doped region formed in said channel region beneath said floating gate and adjoining said first source/drain region, said lightly doped region spaced from the surface of said substrate by said channel region.

Claim 18

A non-volatile memory cell structure comprising: first and second source/drain regions of a first conductivity type formed in the surface of a semiconductor substrate and separated by a channel region of a second conductivity type which is different than said first conductivity type; a floating gate formed over and insulated from said channel region; a control gate formed over and insulated from said floating gate; a lightly doped region formed in said channel region beneath said floating gate and adjoining said first source/drain region, said lightly doped region spaced from the surface of said substrate by said channel region.

Claim 19

The structure of claim 15 wherein said first conductivity type comprises n-type.

Claim 20

The structure of claim 15 wherein said non-volatile memory cell comprises a flash EPROM cell.

Claim 21

The structure of claim 15 wherein said non-volatile memory cell comprises a UV erasable EPROM cell.

Claim 22

The structure of claim 15 and further comprising a pocket region of said second conductivity type, said pocket region formed between said first source/drain region and said channel region.

Claim 23

A memory device disposed in a semiconductor region, said memory device comprising: a data input node; a first supply voltage node disposed within said semiconductor region for providing a first voltage potential; a second supply voltage node disposed within said semiconductor region for providing a second voltage potential; a row decoder for receiving a plurality of row address signals; a column decoder for receiving a plurality of column address signals; an array of non-volatile memory cells for receiving data from said data input node, said memory cells being disposed in rows and columns such that said rows are coupled to said row decoder and said columns are coupled to said column decoder, wherein at least one of said memory cells comprises: a first source/drain region of a first conductivity type formed in the surface of said semiconductor region; a second source/drain region of said first conductivity type formed in the surface of said semiconductor region and separated from said first source/drain region by a channel region; a floating gate formed over and insulated from said channel region; a control gate formed over and insulated from said floating gate; a lightly doped region of said first conductivity type formed in said channel region beneath said floating gate and adjoining said source region, said lightly doped region spaced from the surface of said semiconductor region.

Claim 24

A memory device disposed in a semiconductor region, said memory device comprising: a data input node; a first supply voltage node disposed within said semiconductor region for providing a first voltage potential; a second supply voltage node disposed within said semiconductor region for providing a second voltage potential; a row decoder for receiving a plurality of row address signals; a column decoder for receiving a plurality of column address signals; an array of non-volatile memory cells for receiving data from said data input node, said memory cells being disposed in rows and columns such that said rows are coupled to said row decoder and said columns are coupled to said column decoder, wherein at least one of said memory cells comprises: a first source/drain region of a first conductivity type formed in the surface of said semiconductor region; a second source/drain region of said first conductivity type formed in the surface of said semiconductor region and separated from said first source/drain region by a channel region; a floating gate formed over and insulated from said channel region; a control gate formed over and insulated from said floating gate; a lightly doped region of said first conductivity type formed in said channel region beneath said floating gate and adjoining said source region, said lightly doped region spaced from the surface of said semiconductor region.

Claim 25

The memory device of claim 19 and further comprising a data output node for receiving data from said memory cell array.

Claim 26

The memory device of claim 19 and further comprising read/write circuitry coupled to said row decoder and said column decoder.

Claim 27

The memory device of claim 19 wherein said array of non-volatile memory cells comprises a flash EPROM array.

Claim 28

The memory device of claim 19 wherein said array of non-volatile memory cells comprises a UV erasable EPROM array.

Claim 29

The structure of claim 19 wherein said at least one memory cell further comprises a pocket region said second conductivity type, said pocket region formed between said first source/drain region and said channel region.