Nonvolatile punch through memory cell with buried n+ region in channel

Claim 2

A five terminal nonvolatile punch through memory cell comprising: a. a p type substrate having a surface; b. a first and a second n+ region positioned in spaced apart relationship in the said substrate providing a source and a drain, respectively; c. a very thin oxide layer positioned over a portion of said substrate surface in contacting relationship; d. nitride layer positioned over the said oxide layer in contacting relationship; e. a gate layer positioned over the said nitride layer; and f. an n+ layer buried in the said p type substrate below the said surface of the substrate and substantially between and in spaced apart relationship to the said first and second n+ regions.

Claim 3

A nonvolatile punch through transistor memory cell comprising: a. a p type substrate having a surface; b. a first and a second n+ diffusion area positioned in the said substrate providing, respectively, a source and a drain; c. a vertically justapositioned double dielectric including a very thin oxide layer, the said oxide layer positioned on the surface of the substrate; and d. an isolated n+ region buried in the said substrate below the said surface for injecting charge into the said double dielectric.

Claim 4

A nonvolatile punch through transistor memory cell comprising: a. a p type substrate having a surface; b. a first and a second n+ diffusion area positioned in the said substrate providing, respectively, a source and a drain; c. a vertically justapositioned double dielectric including a very thin oxide layer, the said oxide layer positioned on the surface of the substrate; and d. an isolated n+ region buried in the said substrate below the said surface for injecting charge into the said double dielectric.

Claim 5

A nonvolatile punch through transistor memory cell comprising: a. a p type silicon substrate having a surface; b. a silicon dioxide layer positioned on the surface of the said substrate; c. a silicon nitride layer positioned in cooperation with the said silicon dioxide layer to provide a silicon dioxide thickness between the substrate surface and the said silicon nitride layer less than approximately 100 Angstroms; d. a gate layer positioned on the said silicon nitride layer providing a gate terminal; e. a first n+ diffusion region positioned in the said substrate horizontally to one side of the position of the said silicon nitride layer, providing a source element terminal; f. a second n+ diffusion region positioned in the said substrate in horizontal spaced apart relationship to the said first n+ diffusion region and positioned to the other side of the position of the said silicon nitride layer, providing a drain element terminal; and g. an n+ region positioned approximately 2 microns below the surface of the said substrate, positioned in horizontal spaced apart relationship between the said source and drain elements and in a vertical relationship substantially below the said silicon nitride layer providing a terminal for injecting charge whereby punch through of electrons from the n+ buried region through the said substrate and the said silicon dioxide layer provides a nonvolatile charge in the said silicon nitride layer.

Claim 6

A nonvolatile punch through transistor memory cell comprising: a. a p type silicon substrate having a surface; b. a silicon dioxide layer positioned on the surface of the said substrate; c. a silicon nitride layer positioned in cooperation with the said silicon dioxide layer to provide a silicon dioxide thickness between the substrate surface and the said silicon nitride layer less than approximately 100 Angstroms; d. a gate layer positioned on the said silicon nitride layer providing a gate terminal; e. a first n+ diffusion region positioned in the said substrate horizontally to one side of the position of the said silicon nitride layer, providing a source element terminal; f. a second n+ diffusion region positioned in the said substrate in horizontal spaced apart relationship to the said first n+ diffusion region and positioned to the other side of the position of the said silicon nitride layer, providing a drain element terminal; and g. an n+ region positioned approximately 2 microns below the surface of the said substrate, positioned in horizontal spaced apart relationship between the said source and drain elements and in a vertical relationship substantially below the said silicon nitride layer providing a terminal for injecting charge whereby punch through of electrons from the n+ buried region through the said substrate and the said silicon dioxide layer provides a nonvolatile charge in the said silicon nitride layer.