← Back to Patent Explorer
US3887407A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing semiconductor device with nitride oxide double layer film

Assignee: Hitachi Ltd
•
Filing: 1973-10-17
•
Granted: 1975-06-03
•
Expires: 1993-10-17
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of manufacturing a semiconductor device wherein a silicon nitride film covers the exposed surfaces of an oxide film and the exposed major surface of a semiconductor body, and wherein holes are formed by chemical etching only in the portion of said silicon nitride film directly contacting said major surface, thereby obtaining precise etching of the insulating covering.

Inventors

  • 👤 Minoru Ono
  • 👤 Toshimitu Momoi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 14:48
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10D; H10D99/00; H10P; H10P95/00; H10W74/00; H10W74/40; H10W74/43

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 218 words
A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING THE STEEPS OF: A. FORMING A SEMICONDUCTOR SUBSTRATE WITH A PN JUNCTION THE ENTIRE TERMINATION OF WHICH IS COVERED WITH A FIRST INSULATING FILM CNSISTING ESSENTIALLY OF SILICON DIOXIDE; B. FORMING A HOLE IN THE FIRST INSULATING FILM SO AS TO EXPOSE A SURFACE PORTION OF SAID SEMICONDUCTOR SUBSTRATE, WHILE MAINTANING THE ENTIRE TERMINATION OF SAID PN JUNCTION COVERED WITH SAID FIRST INSULATING FILM; C. COVERING THE ENTIRE EXPOSED UPPER SURFACE OF SAID FIRST INSULATING FILM, THE ENTIRE SIDE WALLS IN SAID HOLE OF SAID FIRST INSULATING FILM, AND THE EXPOSED SURFFACE PORTION OF SAID SEMICONDUCTOR SUBSTRATE WITH A SECOND INSULATING FILM CONSISTING ESSENTIALLY OF SILICON NITRIDE, SO THAT SAID SECOND INSULATING FILM IS SPACED FROM THE TERMINATION OF SAID PN JUNCTION; D. COMPLETELYY COVERING SAID FIRST AND SECOND FILOS, EXCEPT FOR A PORTION OF SAID SECOND FILM DIRECTLY CONTACTING THE SURFACE OF SAID SEMICONDUCTOR SUBSTRATE AT A LOCATION IN SAID HOLE SPACED FROM THE PORTION OF THE SYRFACE COVERED WITH SAID FIRST INSULATING FILM, WITH A CORROSION RESISTIVE MASK; AND E. EXPOSING THE COMBINATION THUS COMPOSED TO AN ETCHANT TO PARTIALLY ETCH AWAY THE PORTION OF SAID SECOND INSULATING FILM NOT COVERED WITH SAID CORROSION RESISTIVE MASK, SO AS NOT TO EXPOSE SAID FIRST INSULATING FILM TO SAID ETCHANT.
Claim 2
Independent Claim 218 words
A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING THE STEEPS OF: A. FORMING A SEMICONDUCTOR SUBSTRATE WITH A PN JUNCTION THE ENTIRE TERMINATION OF WHICH IS COVERED WITH A FIRST INSULATING FILM CNSISTING ESSENTIALLY OF SILICON DIOXIDE; B. FORMING A HOLE IN THE FIRST INSULATING FILM SO AS TO EXPOSE A SURFACE PORTION OF SAID SEMICONDUCTOR SUBSTRATE, WHILE MAINTANING THE ENTIRE TERMINATION OF SAID PN JUNCTION COVERED WITH SAID FIRST INSULATING FILM; C. COVERING THE ENTIRE EXPOSED UPPER SURFACE OF SAID FIRST INSULATING FILM, THE ENTIRE SIDE WALLS IN SAID HOLE OF SAID FIRST INSULATING FILM, AND THE EXPOSED SURFFACE PORTION OF SAID SEMICONDUCTOR SUBSTRATE WITH A SECOND INSULATING FILM CONSISTING ESSENTIALLY OF SILICON NITRIDE, SO THAT SAID SECOND INSULATING FILM IS SPACED FROM THE TERMINATION OF SAID PN JUNCTION; D. COMPLETELYY COVERING SAID FIRST AND SECOND FILOS, EXCEPT FOR A PORTION OF SAID SECOND FILM DIRECTLY CONTACTING THE SURFACE OF SAID SEMICONDUCTOR SUBSTRATE AT A LOCATION IN SAID HOLE SPACED FROM THE PORTION OF THE SYRFACE COVERED WITH SAID FIRST INSULATING FILM, WITH A CORROSION RESISTIVE MASK; AND E. EXPOSING THE COMBINATION THUS COMPOSED TO AN ETCHANT TO PARTIALLY ETCH AWAY THE PORTION OF SAID SECOND INSULATING FILM NOT COVERED WITH SAID CORROSION RESISTIVE MASK, SO AS NOT TO EXPOSE SAID FIRST INSULATING FILM TO SAID ETCHANT.
Claim 3
Independent Claim 218 words
A method of manufacturing a semiconductor device comprising the steps of: a. forming a semiconductor substrate with a PN junction the entire termination of which is covered with a first insulating film consisting essentially of silicon dioxide; b. forming a hole in the first insulating film so as to expose a surface portion of said semiconductor substrate, while maintaining the entire termination of said PN junction covered with said first insulating film; c. covering the entire exposed upper surface of said first insulating film, the entire side walls in said hole of said first insulating film, and the exposed surface portion of said semiconductor substrate with a second insulating film consisting essentially of silicon nitride, so that said second insulating film is spaced from the termination of said PN junction; d. completely covering said first and second films, except for a portion of said second film directly contacting the surface of said semiconductor substrate at a location in said hole spaced from the portion of the surface covered with said first insulating film, with a corrosion resistive mask; and e. exposing the combination thus composed to an etchant to partially etch away the portion of said second insulating film not covered with said corrosion resistive mask, so as not to expose said first insulating film to said etchant.
Claim 4
Independent Claim 218 words
A method of manufacturing a semiconductor device comprising the steps of: a. forming a semiconductor substrate with a PN junction the entire termination of which is covered with a first insulating film consisting essentially of silicon dioxide; b. forming a hole in the first insulating film so as to expose a surface portion of said semiconductor substrate, while maintaining the entire termination of said PN junction covered with said first insulating film; c. covering the entire exposed upper surface of said first insulating film, the entire side walls in said hole of said first insulating film, and the exposed surface portion of said semiconductor substrate with a second insulating film consisting essentially of silicon nitride, so that said second insulating film is spaced from the termination of said PN junction; d. completely covering said first and second films, except for a portion of said second film directly contacting the surface of said semiconductor substrate at a location in said hole spaced from the portion of the surface covered with said first insulating film, with a corrosion resistive mask; and e. exposing the combination thus composed to an etchant to partially etch away the portion of said second insulating film not covered with said corrosion resistive mask, so as not to expose said first insulating film to said etchant.

References Cited (Backward Citations)

US3438873A Cited
US3455020A Cited
US3497407A Cited
US3788913A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-06-02 1978-12-02 1979-06-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-06-02 1982-12-02 1983-06-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-06-02 1986-12-02 1987-06-03 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag