Magnetic random access memory circuit

Claim 2

A magnetic random access memory circuit comprising: a memory cell array having a plurality of sense lines, a plurality of word lines intersecting said plurality of sense lines, a number of magneto-resistive elements located at intersections between said plurality of sense lines and said plurality of word lines, each of said magneto-resistive elements being connected between one sense line and one word line; a plurality of capacitors of the number corresponding to the number of said plurality of sense lines, said plurality of capacitors being previously charged to a high voltage before a reading operation is carried out, each of said plurality of capacitors being connected to a corresponding sense line of said plurality of sense lines through a voltage drop means so that a voltage lower than said high voltage charged in said capacitors is applied to said plurality of sense lines; and means for equalizing the potential of all said plurality of sense lines and all not-selected word lines of said plurality of word lines and for grounding a selected word line of said plurality of word lines so that an electric charge previously stored in said capacitor connected through said voltage drop means to a selected sense line is discharged through said voltage drop means, said selected sense line, a selected magneto-resistive element, and said selected word line, whereby information stored in said selected magneto-resistive element is read out by a potential on said capacitor.

Claim 3

A magnetic random access memory circuit comprising: a memory cell array having a plurality of sense lines, a plurality of word lines intersecting said plurality of sense lines, a number of magneto-resistive elements located at intersections between said plurality of sense lines and said plurality of word lines, each of said magneto-resistive elements being connected between one sense line and one word line; an X peripheral circuit connected to said plurality of word lines and including an X decoder receiving an X address portion of a given address; a Y peripheral circuit connected to said plurality of sense lines and including a Y decoder receiving an Y address portion of said given address; wherein said Y peripheral circuit includes a plurality of pairs of series-connected first and second MOS transistors connected to said plurality of sense lines, respectively, each first MOS transistor having one end connected to a corresponding sense line of said plurality of sense lines, the other end connected to one end of the corresponding second MOS transistor, a gate connected to a reference voltage circuit, each second MOS transistor having the other end connected to a voltage supply and a gate connected to receive a corresponding output of said Y decoder, a connection node between said first MOS transistor and said second MOS transistor being connected to one end of a capacitor having the other end connected to ground, wherein said X peripheral circuit includes a plurality of pairs of series-connected third and fourth MOS transistors having their gates connected to receive a corresponding output of said X decoder so as to operate complementarily to each other, said third MOS transistor having one end connected to a voltage supply and the other end connected to one end of said fourth MOS transistor, the other end of said fourth MOS transistor being connected to ground, a connection node of said third and fourth MOS transistors being connected to a corresponding word line of said plurality of word lines.

Claim 4

A magnetic random access memory circuit comprising: a memory cell array having a plurality of sense lines, a plurality of word lines intersecting said plurality of sense lines, a number of magneto-resistive elements located at intersections between said plurality of sense lines and said plurality of word lines, each of said magneto-resistive elements being connected between one sense line and one word line; an X peripheral circuit connected to said plurality of word lines and including an X decoder receiving an X address portion of a given address; a Y peripheral circuit connected to said plurality of sense lines and including a Y decoder receiving an Y address portion of said given address; wherein said Y peripheral circuit includes a plurality of pairs of series-connected first and second MOS transistors connected to said plurality of sense lines, respectively, each first MOS transistor having one end connected to a corresponding sense line of said plurality of sense lines, the other end connected to one end of the corresponding second MOS transistor, a gate connected to a reference voltage circuit, each second MOS transistor having the other end connected to a voltage supply and a gate connected to receive a corresponding output of said Y decoder, a connection node between said first MOS transistor and said second MOS transistor being connected to one end of a capacitor having the other end connected to ground, wherein said X peripheral circuit includes a plurality of pairs of series-connected third and fourth MOS transistors having their gates connected to receive a corresponding output of said X decoder so as to operate complementarily to each other, said third MOS transistor having one end connected to a voltage supply and the other end connected to one end of said fourth MOS transistor, the other end of said fourth MOS transistor being connected to ground, a connection node of said third and fourth MOS transistors being connected to a corresponding word line of said plurality of word lines.

Claim 5

A magnetic random access memory circuit claimed in claim 2 wherein said Y peripheral circuit includes a plurality of differential amplifiers, each of said differential amplifiers having a pair of inputs connected to a pair of said capacitors connected through a pair of said first MOS transistors to a pair of adjacent sense lines, so that one of a pair of magneto-resistive elements connected to the same word line and to said pair of adjacent sense lines constitutes a memory cell, and the other of said pair of magneto-resistive elements constitutes a reference cell which stores data complementary to data stored in said memory cell, whereby a difference between voltages of said pair of capacitors connected to said pair of adjacent sense lines through said pair of first MOS transistors, respectively, generated dependently upon respective resistance value conditions of said memory cell and said reference cell, is detected by said differential amplifier.

Claim 6

A magnetic random access memory circuit claimed in claim 2 , further including: a second X peripheral circuit provided in symmetry to the first mentioned X peripheral circuit with respect to said Y peripheral circuit, said second X peripheral circuit having the same construction as that of the first mentioned X peripheral circuit; and a second memory cell array provided in symmetry to the first mentioned memory cell array with respect to said Y peripheral circuit, said second memory cell array having the same construction as that of the first mentioned memory cell array; said Y peripheral circuit being in common to the first mentioned memory cell array and said second memory cell array, each of the first mentioned memory cell array and said second memory cell array including a plurality of reference resistors connected between at least one word line and said plurality of sense lines, respectively, wherein when a magneto-resistive element included in one of the first mentioned memory cell array and said second memory cell array, is selected to be read out, the voltage of said capacitor connected to said selected magneto-resistive element through said first MOS transistor is compared with the voltage of said capacitor connected to one reference resistor through said first MOS transistor in the other of the first mentioned memory cell array and said second memory cell array.

Claim 7

A magnetic random access memory circuit claimed in claim 2 , further including a plurality of comparators each having one input connected to said reference voltage circuit, the other input connected to the corresponding sense line, and an output connected to said gate of the corresponding first MOS transistor so that the potential on said corresponding sense line is precisely feedback-controlled on the basis of a reference voltage of said reference voltage circuit.

Claim 8

A magnetic random access memory circuit claimed in claim 2 , wherein each of said magneto-resistive elements is constituted of a tunnel magneto-resistive element.

Claim 9

A magnetic random access memory circuit claimed in claim 2 , wherein each of said magneto-resistive elements is constituted of a giant magneto-resistive element.

Claim 10

A magnetic random access memory circuit comprising: a memory cell array having a plurality of sense lines, a plurality of word lines intersecting said plurality of sense lines, a number of magneto-resistive elements located at intersections between said plurality of sense lines and said plurality of word lines, each of said magneto-resistive elements being connected between one sense line and one word line; an X peripheral circuit connected to said plurality of word lines and including an X decoder receiving an X address portion of a given address; a Y peripheral circuit connected to said plurality of sense lines and including a Y decoder receiving an Y address portion of said given address; wherein said Y peripheral circuit includes: a plurality of pairs of parallel-connected first and second MOS transistors having their gates connected to receive corresponding outputs of said Y decoder, respectively, each of said pairs of first and second MOS transistors being provided for a corresponding one of said plurality of sense lines, one end of each of said first and second MOS transistors being connected to a voltage supply, the other end of said first and second MOS transistors being connected to ground through a first capacitor and a second capacitor, respectively; a plurality of pairs of series-connected third and fourth MOS transistors having their gates connected to receive a corresponding output of said Y decoder so as to operate complementarily to each other, each pair of said pairs of series-connected third and fourth MOS transistors being connected between the other end of the corresponding first MOS transistor and the other end of the corresponding second MOS transistor; and a plurality of fifth MOS transistors having their gates connected to a reference voltage circuit, each of said plurality of fifth MOS transistors having one end connected to a connection node between the corresponding seventh and eighth MOS transistors, and the other end connected to a corresponding sense line of said plurality of sense lines, whereby a voltage on the connection node between said first capacitor and the corresponding first MOS transistor and a voltage on the connection node between said second capacitor and the corresponding second MOS transistor are compared for reading out data on a selected magneto-resistive element connected to the corresponding sense line, wherein said X peripheral circuit includes a plurality of pairs of series-connected sixth and seventh MOS transistors having their gate connected to receive a corresponding output of said X decoder so as to operate complementarily to each other, said sixth MOS transistor having one end connected to a voltage supply and the other end connected to one end of said seventh MOS transistor, the other end of said seventh MOS transistor being connected to ground, a connection node of said sixth and eleventh MOS transistors being connected to a corresponding word line of said plurality of word lines, wherein the magnetic random access memory circuit further includes a timing controller for controlling respective operation timings of said X decoder and said Y decoder.

Claim 11

A magnetic random access memory circuit comprising: a memory cell array having a plurality of sense lines, a plurality of word lines intersecting said plurality of sense lines, a number of magneto-resistive elements located at intersections between said plurality of sense lines and said plurality of word lines, each of said magneto-resistive elements being connected between one sense line and one word line; an X peripheral circuit connected to said plurality of word lines and including an X decoder receiving an X address portion of a given address; a Y peripheral circuit connected to said plurality of sense lines and including a Y decoder receiving an Y address portion of said given address; wherein said Y peripheral circuit includes: a plurality of pairs of parallel-connected first and second MOS transistors having their gates connected to receive corresponding outputs of said Y decoder, respectively, each of said pairs of first and second MOS transistors being provided for a corresponding one of said plurality of sense lines, one end of each of said first and second MOS transistors being connected to a voltage supply, the other end of said first and second MOS transistors being connected to ground through a first capacitor and a second capacitor, respectively; a plurality of pairs of series-connected third and fourth MOS transistors having their gates connected to receive a corresponding output of said Y decoder so as to operate complementarily to each other, each pair of said pairs of series-connected third and fourth MOS transistors being connected between the other end of the corresponding first MOS transistor and the other end of the corresponding second MOS transistor; and a plurality of fifth MOS transistors having their gates connected to a reference voltage circuit, each of said plurality of fifth MOS transistors having one end connected to a connection node between the corresponding seventh and eighth MOS transistors, and the other end connected to a corresponding sense line of said plurality of sense lines, whereby a voltage on the connection node between said first capacitor and the corresponding first MOS transistor and a voltage on the connection node between said second capacitor and the corresponding second MOS transistor are compared for reading out data on a selected magneto-resistive element connected to the corresponding sense line, wherein said X peripheral circuit includes a plurality of pairs of series-connected sixth and seventh MOS transistors having their gate connected to receive a corresponding output of said X decoder so as to operate complementarily to each other, said sixth MOS transistor having one end connected to a voltage supply and the other end connected to one end of said seventh MOS transistor, the other end of said seventh MOS transistor being connected to ground, a connection node of said sixth and eleventh MOS transistors being connected to a corresponding word line of said plurality of word lines, wherein the magnetic random access memory circuit further includes a timing controller for controlling respective operation timings of said X decoder and said Y decoder.

Claim 12

A magnetic random access memory circuit claimed in claim 8 , further including a plurality of comparators each having one input connected to said reference voltage circuit, the other input connected to the corresponding sense line, and an output connected to said gate of the corresponding fifth MOS transistor so that the potential on said corresponding sense line is precisely feedback-controlled on the basis of a reference voltage of said reference voltage circuit.

Claim 13

A magnetic random access memory circuit claimed in claim 8 , wherein each of said magneto-resistive elements is constituted of a tunnel magneto-resistive element.

Claim 14

A magnetic random access memory circuit claimed in claim 8 , wherein each of said magneto-resistive elements is constituted of a giant magneto-resistive element.