Method for forming high capacitance memory cells

Claim 1

A method for forming a trench capacitor, comprising: forming a trench having an interior surface in a silicon substrate; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of silicon pillars, wherein the array of silicon pillars have an average center to center spacing of 20 nanometers (nm); removing the self-structured mask; forming an insulator layer outwardly from the array of silicon pillars; and forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench.

Claim 2

A method for forming a trench capacitor, comprising: forming a trench having an interior surface in a silicon substrate; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of silicon pillars, wherein the array of silicon pillars have an average center to center spacing of 20 nanometers (nm); removing the self-structured mask; forming an insulator layer outwardly from the array of silicon pillars; and forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench.

Claim 6

A method for forming a trench capacitor, comprising: forming a trench having an interior surface in a silicon substrate; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of silicon pillars; removing the self-structured mask; forming an insulator layer outwardly from the array of silicon pillars; and forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench, wherein etching the interior surface includes controlling the temperature of the substrate to a negative (-) 130 degrees Celsius.

Claim 7

A method for forming a trench capacitor, comprising: forming a trench having an interior surface in a silicon substrate; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of silicon pillars; removing the self-structured mask; forming an insulator layer outwardly from the array of silicon pillars; and forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench, wherein etching the interior surface includes controlling the temperature of the substrate to a negative (-) 130 degrees Celsius.

Claim 8

A method for forming a memory cell with a trench capacitor, comprising: forming a transistor including first and second source/drain regions, a body region and a gate in a layer of semiconductor material on a substrate; forming a trench having an interior surface in the layer of semiconductor material; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of asperities, wherein the array of asperities have an average center to center spacing of 20 nanometers (nm); removing the self-structured mask; forming an insulator layer outwardly from the array of asperities; forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench such that the polycrystalline semiconductor plate forms one of the plates of the trench capacitor; and coupling the trench capacitor to one of the source/drain regions of the transistor.

Claim 9

A method for forming a memory cell with a trench capacitor, comprising: forming a transistor including first and second source/drain regions, a body region and a gate in a layer of semiconductor material on a substrate; forming a trench having an interior surface in the layer of semiconductor material; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of asperities, wherein the array of asperities have an average center to center spacing of 20 nanometers (nm); removing the self-structured mask; forming an insulator layer outwardly from the array of asperities; forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench such that the polycrystalline semiconductor plate forms one of the plates of the trench capacitor; and coupling the trench capacitor to one of the source/drain regions of the transistor.

Claim 17

A method for forming a memory cell with a trench capacitor, comprising: forming a transistor including first and second source/drain regions, a body region and a gate in a layer of semiconductor material on a substrate; forming a trench having an interior surface in the layer of semiconductor material; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of asperities; removing the self-structured mask; forming an insulator layer outwardly from the array of asperities; forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench such that the polycrystalline semiconductor plate forms one of the plates of the trench capacitor; and coupling the trench capacitor to one of the source/drain regions of the transistor, wherein etching the interior surface includes controlling the temperature of the substrate to a negative (-) 130 degrees Celsius.

Claim 18

A method for forming a memory cell with a trench capacitor, comprising: forming a transistor including first and second source/drain regions, a body region and a gate in a layer of semiconductor material on a substrate; forming a trench having an interior surface in the layer of semiconductor material; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of asperities; removing the self-structured mask; forming an insulator layer outwardly from the array of asperities; forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench such that the polycrystalline semiconductor plate forms one of the plates of the trench capacitor; and coupling the trench capacitor to one of the source/drain regions of the transistor, wherein etching the interior surface includes controlling the temperature of the substrate to a negative (-) 130 degrees Celsius.

Claim 19

A method for forming a memory cell with a trench capacitor, comprising: forming a transistor including first and second source/drain regions, a body region and a gate in a layer of semiconductor material on a substrate, wherein forming a transistor comprises forming a transistor with first and second source drain regions that are vertically aligned with the body region; forming a trench having an interior surface in the layer of semiconductor material; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of asperities, wherein the array of asperities have an average center to center spacing of 20 nanometers (nm); removing the self-structured mask; forming an insulator layer outwardly from the array of asperities; forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench such that the polycrystalline semiconductor plate forms one of the plates of the trench capacitor; and coupling the trench capacitor to one of the source/drain regions of the transistor.

Claim 20

A method for forming a memory cell with a trench capacitor, comprising: forming a transistor including first and second source/drain regions, a body region and a gate in a layer of semiconductor material on a substrate, wherein forming a transistor comprises forming a transistor with first and second source drain regions that are vertically aligned with the body region; forming a trench having an interior surface in the layer of semiconductor material; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of asperities, wherein the array of asperities have an average center to center spacing of 20 nanometers (nm); removing the self-structured mask; forming an insulator layer outwardly from the array of asperities; forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench such that the polycrystalline semiconductor plate forms one of the plates of the trench capacitor; and coupling the trench capacitor to one of the source/drain regions of the transistor.

Claim 21

A method for forming a trench capacitor, comprising: forming a trench having an interior surface in a silicon substrate; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of silicon pillars, wherein etching the interior surface of the trench includes performing a dry etch in the presence of a sulfur hexafluoride (SF 6 ) gas and controlling the temperature of the substrate; removing the self-structured mask; forming an insulator layer outwardly from the array of silicon pillars, wherein forming an insulator layer includes depositing the oxide layer using atomic layer epitaxy (ALE); and forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench.

Claim 22

A method for forming a trench capacitor, comprising: forming a trench having an interior surface in a silicon substrate; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of silicon pillars, wherein etching the interior surface of the trench includes performing a dry etch in the presence of a sulfur hexafluoride (SF 6 ) gas and controlling the temperature of the substrate; removing the self-structured mask; forming an insulator layer outwardly from the array of silicon pillars, wherein forming an insulator layer includes depositing the oxide layer using atomic layer epitaxy (ALE); and forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench.

Claim 23

A method for forming a trench capacitor, comprising: forming a trench having an interior surface in a silicon substrate; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of silicon pillars, wherein etching the interior surface of the trench includes performing a dry etch in the presence of a sulfur hexafluoride (SF 6 ) gas and controlling the temperature of the substrate; removing the self-structured mask; forming an insulator layer outwardly from the array of silicon pillars, wherein forming an insulator layer includes depositing the oxide layer using atomic layer epitaxy (ALE); forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench; and wherein the sputtering an alloy onto the interior surface of the trench includes forming AuPd alloy islands having diameters of less than 10 nm on 20 nm centers.

Claim 24

A method for forming a trench capacitor, comprising: forming a trench having an interior surface in a silicon substrate; forming a self-structured mask in the trench, wherein forming a self-structured mask comprises sputtering an alloy onto the interior surface of the trench; etching the interior surface of the trench to form an array of silicon pillars, wherein etching the interior surface of the trench includes performing a dry etch in the presence of a sulfur hexafluoride (SF 6 ) gas and controlling the temperature of the substrate; removing the self-structured mask; forming an insulator layer outwardly from the array of silicon pillars, wherein forming an insulator layer includes depositing the oxide layer using atomic layer epitaxy (ALE); forming a polycrystalline semiconductor plate outwardly from the insulator layer in the trench; and wherein the sputtering an alloy onto the interior surface of the trench includes forming AuPd alloy islands having diameters of less than 10 nm on 20 nm centers.