Dynamic RAM having 3-dimensional memory cell structure

Claim 1

A semiconductor memory device comprising: a substrate; first semiconductor regions of a first conductivity type formed in a column configuration on said substrate and acting as a storage node electrode, the arrangement of said first semiconductor regions being such that the spaces between first semiconductor regions in a first direction differ from those in a second direction essentially perpendicular to the first direction, the spaces in the second direction being 2λ or more in the case where the spaces in the first direction are λ; a capacitor insulation films formed on the side walls of said first semiconductor regions; second semiconductor regions of the first conductivity type formed with said capacitor insulation films disposed between said second semiconductor regions and the side walls of said first semiconductor regions and acting as a cell plate electrode; third semiconductor regions of a second conductivity type formed in an annular configuration on the upper portions of said first semiconductor regions and acting as a channel region, said third semiconductor regions having a thickness of 2000 angstroms or less; gate insulation films formed in the inner and outer side walls of said third semiconductor regions; word lines, formed in the first direction, with said gate insulation films disposed between said word lines and the inner and outer side walls of said third semiconductor regions, said word lines serving as transfer gate electrodes; fourth semiconductor regions of the first conductivity type formed in areas near the end portions of openings of said third annular semiconductor regions; and bit lines, formed in the second direction and in contact with said fourth semiconductor regions.