US5401681A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming a bit line over capacitor array of memory cells
Assignee: Micron Technology Inc
•
Filing: 1994-07-20
•
Granted: 1995-03-28
•
Expires: 2014-07-20
Abstract
Abstract A method of forming a bit line over capacitor array of memory cells includes, a) providing an array of word lines; b) providing active areas about the word lines to define an array of memory cell FETs; c) providing a layer of electrically insulating material over the word lines and active areas; d) providing first and second respective contact openings through the insulating material layer to capacitor and bit contact active regions; e) providing electrically conductive material within the first and second contact openings which electrically connects with the respective capacitor and bit active regions, with the electrically conductive material within the respective first and second contact openings collectively extending elevationally over and above the insulating material upper surface, the electrically conductive material within the first contact openings electrically connecting with the electrically conductive material of the second contact openings above the insulating material upper surface; and f) in a single step, chemical-mechanical polishing the collective electrically conductive material extending over and above the insulating material upper surface downwardly to at least the upper surface of the insulating material, the single chemical-mechanical polishing step effectively electrically isolating the conductive material within the first contact openings from the conductive material within the second contact openings.
Inventors
- 👤 Charles H. Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:34
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10W; H10W20/00; H10W20/01; H10D1/712; H10D1/714; H10D1/716
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
253 words
A method of forming a bit line over capacitor array of memory cells comprising the following steps: providing rant array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a layer of electrically insulating material over the word lines and active areas, the layer of insulating material having an upper surface which is above the word lines; providing first and second respective contact openings through the insulating material layer to the respective first and second active regions; providing electrically conductive material within the first and second contact openings which electrically connects with the respective first and second active regions, the electrically conductive material within the respective first and second contact openings collectively extending elevationally over and above the insulating material upper surface, the electrically conductive material within the first contact openings electrically connecting with the electrically conductive material of the second contact openings above the insulating material upper surface; and in a single step, chemical-mechanical polishing the collective electrically conductive material extending over and above the insulating material upper surface downwardly to at least the upper surface of the insulating material, the single chemical-mechanical polishing step effectively electrically isolating the conductive material within the first contact openings from the conductive material within the second contact openings.
Claim 2
Independent Claim
253 words
A method of forming a bit line over capacitor array of memory cells comprising the following steps: providing rant array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a layer of electrically insulating material over the word lines and active areas, the layer of insulating material having an upper surface which is above the word lines; providing first and second respective contact openings through the insulating material layer to the respective first and second active regions; providing electrically conductive material within the first and second contact openings which electrically connects with the respective first and second active regions, the electrically conductive material within the respective first and second contact openings collectively extending elevationally over and above the insulating material upper surface, the electrically conductive material within the first contact openings electrically connecting with the electrically conductive material of the second contact openings above the insulating material upper surface; and in a single step, chemical-mechanical polishing the collective electrically conductive material extending over and above the insulating material upper surface downwardly to at least the upper surface of the insulating material, the single chemical-mechanical polishing step effectively electrically isolating the conductive material within the first contact openings from the conductive material within the second contact openings.
Claim 3
Dependent Claim
51 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein all of the electrically conductive material within the first contact openings is of the same composition as all of the electrically conductive material within the second contact openings during the single chemical-mechanical polishing step.
Claim 4
Dependent Claim
25 words
The method of forming a bit line over capacitor array of memory cells of claim 2 wherein the electrically conductive material is conductively doped polysilicon.
Claim 5
Dependent Claim
71 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein all of the electrically conductive material within the first contact openings is of the same composition as all of the electrically conductive material within the second contact openings during the single chemical-mechanical polishing step, the electrically conductive material being everywhere homogeneous within the first and second contact openings during the single chemical-mechanical polishing step.
Claim 6
Dependent Claim
25 words
The method of forming a bit line over capacitor array of memory cells of claim 4 wherein the electrically conductive material is conductively doped polysilicon.
Claim 7
Dependent Claim
50 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein overall composition of the electrically conductive material within the first contact openings is different from overall composition of the electrically conductive material within the second contact openings during the single chemical-mechanical polishing step.
Claim 8
Dependent Claim
89 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein overall composition of the electrically conductive material within the first contact openings is different from overall composition of the electrically conductive material within the second contact openings during the single chemical-mechanical polishing step, the composition of material within the second contact openings being homogeneous within the second contact openings during the single chemical-mechanical polishing step, the composition of material within the first contact openings being non-homogeneous during the single chemical-mechanical polishing step.
Claim 9
Dependent Claim
40 words
The method of forming a bit line over capacitor array of memory cells of claim 1 further comprising removing electrically conductive material extending over and above the insulating material upper surface downwardly to below the upper surface of insulating material.
Claim 10
Dependent Claim
135 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the electrically conductive material within the second contact openings is homogeneous within the second contact openings during the single chemical-mechanical polishing step and extends outwardly over the insulating material upper surface; the electrically conductive material within the first contact openings comprising a capacitor storage node layer within the array, the capacitor storage node layer less than completely filling the first contact openings, the capacitor storage node layer and electrically conductive material extending outwardly of the second contact openings overlapping one another over the insulating material upper surface; and the single chemical-mechanical polishing step being conducted to define isolated capacitor storage nodes within the first contact openings and to define conductive plugs extending upwardly from the second active regions.
Claim 11
Dependent Claim
128 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the electrically conductive material within the second contact openings is homogeneous within the second contact openings during the single chemical-mechanical polishing step and extends outwardly over the insulating material upper surface; the electrically conductive material within the first contact openings comprising a capacitor storage node layer within the array, the capacitor storage node layer less than completely filling the first contact openings, the capacitor storage node layer outwardly overlying the electrically conductive material extending outwardly of the second contact openings; and the single chemical-mechanical polishing step being conducted to define isolated capacitor storage nodes within the first contact openings and to define conductive plugs extending upwardly from the second active regions.
Claim 12
Dependent Claim
182 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the steps of providing electrically conductive material and single step chemical-mechanical polishing comprise: providing a first layer of conductive material which overfills the first and second contact openings; photopatterning the first layer to define a respective mask openings over the first active regions; etching the first layer of conductive material through the mask openings selectively relative to the insulating material layer; etching the :insulating material layer through the mask openings to define a respective third contact openings which overlap with the first contact openings; depositing an electrically conductive capacitor storage node layer over the first layer of conductive material and to within the third contact openings, the electrically conductive capacitor storage node layer electrically connecting with the first active regions; and single step chemical-mechanical polishing the capacitor storage node layer and first layer downwardly to at least the insulating layer outer surface to define isolated capacitor storage nodes within the first contact openings and to define conductive plugs extending upwardly from the second active regions.
Claim 13
Dependent Claim
157 words
The method of forming a bit line over capacitor array of memory cells of claim 1 further comprising, after the single step chemical-mechanical polishing, depositing a layer of masking material over the electrically conductive material within the first contact openings; then, depositing a layer of hemispherical grain polysilicon over the masking material; partial blanket etching through the hemispherical grain polysilicon over the electrically conductive material within the first contact openings selectively relative to the masking material to define a hemispherical grain polysilicon archipelago mask; etching the masking material selectively relative to the polysilicon archipelago mask to form an archipelago mask of the masking material; etching into the electrically conductive material within the first contact openings selectively relative to the masking material archipelago mask to form substantially vertical villus bars of electrically conductive material within the first contact openings; and providing a capacitor dielectric and a capacitor cell layer over the villus bars to define memory cell capacitors.
Claim 14
Dependent Claim
23 words
The method of forming a bit line over capacitor array of memory cells of claim 12 wherein the masking material comprises silicon dioxide.
Claim 15
Dependent Claim
234 words
The method of forming a bit line over capacitor array of memory cells of claim 1 further comprising: removing electrically conductive material extending over and above the insulating material upper surface downwardly within the first contact openings to below the upper surface of insulating material to recess the electrically conductive material within the first contact openings, the respective recesses defining an edge of insulating material within the respective first contact openings; and after the single step chemical-mechanical polishing, depositing a layer of masking material over the recessed electrically conductive material within the first contact openings; then, depositing a layer of hemispherical grain polysilicon over the masking material; partial blanket etching through the hemispherical grain polysilicon over the electrically conductive material within the first contact openings selectively relative to the masking material to define a hemispherical grain polysilicon archipelago mask; etching the masking material selectively relative to the polysilicon archipelago mask to form an archipelago mask of the masking material, the archipelago mask comprising masking material positioned over the electrically conductive material within the first contact openings against the respective recess edges; etching into the electrically conductive material within the first contact openings selectively relative to the masking material archipelago mask to form substantially vertical villus bars of electrically conductive material within the, first contact openings; and providing a capacitor dielectric and a capacitor cell layer over the villus bars to define memory cell capacitors.
Claim 16
Dependent Claim
23 words
The method of forming a bit line over capacitor array of memory cells of claim 14 wherein the masking material comprises silicon dioxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-27 | 1998-09-26 | 1999-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-27 | 2002-09-26 | 2003-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-27 | 2006-09-26 | 2007-03-28 | $7700.00 | Window Closed / Lapsed |