Method of fabricating a vertical FET device with low gate to drain overlap capacitance

Abstract

Abstract This is a vertical MOSFET device with low gate to drain overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24,26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, and a gate electrode 36 surrounding the vertical pillar not substantially extending into the highly doped drain contact region 30. This is also a method of forming a vertical MOSFET device on a single crystal semiconductor substrate, the device having a pillar on the substrate, with the pillar having a channel region in a lower portion and with the channel region having a top and a highly doped first source/drain region in an upper portion of the pillar, with the substrate having a highly doped second source/drain region and with a gate insulator on the substrate and on the pillar. The method comprises: isotropically forming a gate electrode material layer on the pillar and the substrate; anisotropically depositing a gate height determining insulator material on horizontal surfaces to at least the top of the channel region but not substantially overlapping the first highly doped source/drain region; and etching exposed gate electrode material to remove exposed gate electrode material above the gate height determining insulator material.

Inventors

• 👤 Mark S. Rodder

Bibliographic Details