Cross-point lightly-doped drain-source trench transistor and fabrication process therefor

Claim 1

A self-aligned, slightly-doped drain/source field effect trench transistor device comprising: a substrate having a lower portion of heavily doped n+ conductivity semiconductor material, the upper portion of said substrate being light doped n- conductivity epitaxial semiconductor material, said upper lightly doped portion being less conductive than said heavily doped lower portion, a well region formed with p-type dopants disposed in said upper portion of said substrate. at least one polysilicon filled trench extending from the surface of said well region and into said well region, said trench being electrically isolated from said well region by a layer of gate oxide insulation on the bottom and sidewalls of said trench between the well region and said polysilicon in said trench, a source junction region located in said well region beneath the bottom surface of said trench, a diffusion region forming a first drain junction region disposed in said well region, said first drain junction region being heavily doped with n++ type dopants, said first drain junction region being located on the surface of said well regional surrounding said trench, a second lightly-doped drain junction region lightly doped with n+ type dopants in said well region proximate said first drain junction region and being self-aligned with the upper portion of said sidewalls of said trench, and a polysilicon word line element disposed over said polysilicon filled trench.