US4466178A
Expired / Lapsed
US
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Method of making extremely small area PNP lateral transistor by angled implant of deep trenches followed by refilling the same with dielectrics
Assignee: Conexant Systems LLC
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Filing: 1981-06-25
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Granted: 1984-08-21
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Expires: 2001-06-25
Abstract
Abstract An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope the substrate within the active region. The P type substrate is double energy arsenic planted through one surface to establish a N region to a given depth. This surface is oxidized and photoresist masked conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. P+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy N implanted depth. Drive-in diffusion enlarges the P+ areas for the emitter and collector and oxidation fills the moat insulating regions around the active area. The oxide is stripped and the N region enhanced to N+ at the surface, with silox being deposited and opened for metal contacts to the N+ region for the base and the emitter and collector regions. The doping profile of the base region provides a potential barrier to minimize the flow of electrons toward the surface because the emitter electrons are channeled through the less heavily doped part of the base region to the collector.
Inventors
- 👤 Sidney I. Soclof
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:09
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/60; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
180 words
A method for forming an array of sub-micron dimensioned PNP lateral transistors on a substrate doped P type, wherein each transistor is formed comprising the following steps: implanting N type impurities into the substrate for a given depth; masking the substrate to outline boundary regions for each active region to comprise a transistor; slotting the substrate in said boundary region beyond said depth; doping the substrate via the slotted boundary regions to a depth less than said depth to render regions of the substrate adjacent the boundary regions above said depth P+ doped; said doping being achieved by ion implant at angles to the direction of the slot such that the implanting is confined to upper portions of each slot above said given depth due to shadow effect; filling the doped slotted boundary regions with field oxide; doping the active region of each transistor N+ type adjacent the substrate surface which is slotted except for the P+ portions thereof; metallizing and patterning said substrate surface to provide electrical connections to each of said P+ regions and to said N+ region.
Claim 2
Independent Claim
180 words
A method for forming an array of sub-micron dimensioned PNP lateral transistors on a substrate doped P type, wherein each transistor is formed comprising the following steps: implanting N type impurities into the substrate for a given depth; masking the substrate to outline boundary regions for each active region to comprise a transistor; slotting the substrate in said boundary region beyond said depth; doping the substrate via the slotted boundary regions to a depth less than said depth to render regions of the substrate adjacent the boundary regions above said depth P+ doped; said doping being achieved by ion implant at angles to the direction of the slot such that the implanting is confined to upper portions of each slot above said given depth due to shadow effect; filling the doped slotted boundary regions with field oxide; doping the active region of each transistor N+ type adjacent the substrate surface which is slotted except for the P+ portions thereof; metallizing and patterning said substrate surface to provide electrical connections to each of said P+ regions and to said N+ region.
Claim 3
Dependent Claim
25 words
The method of claim 1, wherein: said slotting is achieved by one of ion milling and ODE etching for a (110) surface of said substrate.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein: said implanting is a double energy arsenic implant.
Claim 5
Dependent Claim
18 words
The method of claim 1, wherein: said last mentioned doping is driven into the active region by heat.
Claim 6
Dependent Claim
39 words
The method of claim 1, wherein: said metallization and patterning is achieved by depositing a layer of silicon oxide over the substrate, and opening contact areas to each of said P+ regions and to said N+ region for metallization.
Claim 7
Independent Claim
138 words
The method of making a PNP lateral transistor in a P doped substrate, consisting of the steps of: implanting the substrate N type using double energy implants to a certain depth, forming a continuous trench in the substrate bounding the region for the transistor and penetrating said depth; P+ doping opposed spaced apart portions of said region above said certain depth by ion implant across opposed portions of the trench at angles to the directions of the opposed trench portions such that the implanting is confined to the regions above said depth due to shadow effect; N+ doping the non P+ doped portions of said region adjacent the recessed substrate surface; filling said recess with field oxide; and establishing electrical connections to each of said P+ spaced apart portions and to the N+ doped portion of said region.
Claim 8
Independent Claim
138 words
The method of making a PNP lateral transistor in a P doped substrate, consisting of the steps of: implanting the substrate N type using double energy implants to a certain depth, forming a continuous trench in the substrate bounding the region for the transistor and penetrating said depth; P+ doping opposed spaced apart portions of said region above said certain depth by ion implant across opposed portions of the trench at angles to the directions of the opposed trench portions such that the implanting is confined to the regions above said depth due to shadow effect; N+ doping the non P+ doped portions of said region adjacent the recessed substrate surface; filling said recess with field oxide; and establishing electrical connections to each of said P+ spaced apart portions and to the N+ doped portion of said region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-21 | 1988-02-20 | 1988-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-21 | 1992-02-20 | 1992-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-21 | 1996-02-20 | 1996-08-21 | $7700.00 | Window Closed / Lapsed |