US4651184A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dram cell and array
Assignee: Texas Instruments Inc
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Filing: 1984-08-31
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Granted: 1987-03-17
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Expires: 2004-08-31
Abstract
Abstract A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bit line on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. A ground line runs past the transistor gate in the upper portion of the trench down into the lower portion of the trench to form the other capacitor plate.
Inventors
- 👤 Satwinder S. Malhi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:16
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
152 words
A memory cell comprising: a substrate having a first conductivity type, having a first cavity formed therein and having a second cavity formed therein contiguous with said first cavity and extending farther into said substrate than said first cavity; a first conductive region formed in said second cavity but insulated from said substrate; a first doped region of a second conductivity type formed in said substrate adjacent to said second cavity; a second doped region of said second conductivity type formed in said substrate adjacent to and surrounding the portion of said second cavity extending from said first cavity into said substrate, and adjacent to said first cavity but disposed away from said first doped region, defining a channel region in said substrate between said first and second doped regions; and a second conductive region formed in said first cavity but insulated from said substrate and insulated from said first conductive region.
Claim 2
Dependent Claim
152 words
A memory cell comprising: a substrate having a first conductivity type, having a first cavity formed therein and having a second cavity formed therein contiguous with said first cavity and extending farther into said substrate than said first cavity; a first conductive region formed in said second cavity but insulated from said substrate; a first doped region of a second conductivity type formed in said substrate adjacent to said second cavity; a second doped region of said second conductivity type formed in said substrate adjacent to and surrounding the portion of said second cavity extending from said first cavity into said substrate, and adjacent to said first cavity but disposed away from said first doped region, defining a channel region in said substrate between said first and second doped regions; and a second conductive region formed in said first cavity but insulated from said substrate and insulated from said first conductive region.
Claim 3
Dependent Claim
17 words
A memory cell as in claim 1 wherein said first and second conductive regions comprise polycrystalline silicon.
Claim 4
Dependent Claim
22 words
A memory cell as in claim 1 wherein said first and second conductive regions are insulated from said substrate by a dielectric.
Claim 5
Dependent Claim
25 words
A memory cell as in claim 3 wherein said dielectric is chosen from the group of silicon dioxide and silicon nitride or a combination thereof.
Claim 6
Dependent Claim
13 words
A memory cell as in claim 1 wherein said substrate comprises crystalline silicon.
Claim 7
Dependent Claim
195 words
A memory array comprising: a substrate having a first conductivity type; a first group of substantially parallel conductive leads formed on the surface of said substrate; a second group of substantially parallel conductive leads formed on the surface of said substrate defining crosspoints with the intersections with said first group of conductive leads; a memory cell formed at a pluraity of said crosspoints in a first cavity formed therein and having a second cavity formed therein contiguous with said first cavity and extending farther into said substrate than said first cavity, each of said memory cells comprising: (a) a first conductive region formed in said second cavity but insulated from said substrate; (b) a first doped region of a second conductivity type formed in said substrate adjacent to said second cavity; (c) a second doped region of said second conductivity type formed in said substrate adjacent to said first cavity but disposed away from said first doped region, defining a channel region in said substrate between said first and second doped regions; and (d) a second conductive region formed in said first cavity but insulated form said substrate and insulated from said first conductive region.
Claim 8
Dependent Claim
195 words
A memory array comprising: a substrate having a first conductivity type; a first group of substantially parallel conductive leads formed on the surface of said substrate; a second group of substantially parallel conductive leads formed on the surface of said substrate defining crosspoints with the intersections with said first group of conductive leads; a memory cell formed at a pluraity of said crosspoints in a first cavity formed therein and having a second cavity formed therein contiguous with said first cavity and extending farther into said substrate than said first cavity, each of said memory cells comprising: (a) a first conductive region formed in said second cavity but insulated from said substrate; (b) a first doped region of a second conductivity type formed in said substrate adjacent to said second cavity; (c) a second doped region of said second conductivity type formed in said substrate adjacent to said first cavity but disposed away from said first doped region, defining a channel region in said substrate between said first and second doped regions; and (d) a second conductive region formed in said first cavity but insulated form said substrate and insulated from said first conductive region.
Claim 9
Dependent Claim
17 words
A memory array as in claim 6 wherein said first and second conductive regions comprise polycrystalline silicon.
Claim 10
Dependent Claim
22 words
A memory array as in claim 6 wherein said first and second conductive regions are insulated from said substrate by a dielectric.
Claim 11
Dependent Claim
25 words
A memory array as in claim 8 wherein said dielectric is chosen from the group of silicon dioxide and silicon nitride or a combination thereof.
Claim 12
Dependent Claim
13 words
A memory array as in claim 6 wherein said substrate comprises crystalline silicon.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1990-03-16 | 1990-09-15 | 1991-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-16 | 1994-09-15 | 1995-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-16 | 1998-09-15 | 1999-03-17 | $7700.00 | Window Closed / Lapsed |