High speed double polycide bipolar/CMOS integrated circuit process

Claim 1

A method of fabricating a mixed process integrated circuit including a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar transistor on a common substrate, comprising the following steps, steps (f) and (g) not necessarily being in the order stated: (a) providing a substrate of semiconductor material having a main face and containing impurity atoms that provide charge carriers of a first polarity; (b) forming and patterning a first conductive layer to provide: (i) an elongate insulated gate structure of a predetermined height for the MOSFET on a first portion of the main face of said substrate, and first and second areas of the main face exposed along first and second opposite sides respectively of the gate structure, and (ii) a base contact structure for the bipolar transistor on a second portion of the main face of the substrate in contact with the semiconductor material, including first and second base contact portions having opposed third and fourth sides spaced apart about a third exposed area of the main face; (c) introducing impurity atoms that provide charge carriers of a second polarity, opposite the first polarity, into the substrate by way of said first and second areas of the main face to form a lightly-doped drain region in the MOSFET, the gate structure being effective to mask the region of the substrate immediately subjacent the gate structure from the impurity atoms; (d) forming a sidewall of a material that is opaque to atoms of a selected impurity along said first and second sides of the gate structure, and said third and fourth sides of the base contact structure, whereby a strip of the main face along each said side of the gate structure and base contact structure is covered by the sidewall but other parts of the first, second and third areas of the main face remain exposed; (e) introducing atoms of the selected impurity into the substrate by way of those portions of the first, second and third areas which are exposed adjacent said sidewalls, the atoms of said selected impurity providing charge carriers of said second polarity to form heavily doped source and drain regions under the first and second areas in the MOSFET and a base region under the third area in the bipolar transistor; (f) forming a second layer of conductive material over said exposed portions of said first, second and third areas, and over the gate structure; (g) removing the conductive material of said second layer over the gate structure that is at a height over the main face that is at least as great as the height of the gate structure so as to form two discrete source and drain contacts for the MOSFET overlying said first and second areas respectively of the main face; (h) forming an emitter in the substrate under the third area for the bipolar transistor; and (i) the portion of the second conductive layer formed over the exposed third area serving as an emitter contact so that complete, operative bipolar and MOSFET devices are fabricated on a common substrate with only two layers of conductive material.

Claim 2

A method of fabricating a mixed process integrated circuit including a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar transistor on a common substrate, comprising the following steps, steps (f) and (g) not necessarily being in the order stated: (a) providing a substrate of semiconductor material having a main face and containing impurity atoms that provide charge carriers of a first polarity; (b) forming and patterning a first conductive layer to provide: (i) an elongate insulated gate structure of a predetermined height for the MOSFET on a first portion of the main face of said substrate, and first and second areas of the main face exposed along first and second opposite sides respectively of the gate structure, and (ii) a base contact structure for the bipolar transistor on a second portion of the main face of the substrate in contact with the semiconductor material, including first and second base contact portions having opposed third and fourth sides spaced apart about a third exposed area of the main face; (c) introducing impurity atoms that provide charge carriers of a second polarity, opposite the first polarity, into the substrate by way of said first and second areas of the main face to form a lightly-doped drain region in the MOSFET, the gate structure being effective to mask the region of the substrate immediately subjacent the gate structure from the impurity atoms; (d) forming a sidewall of a material that is opaque to atoms of a selected impurity along said first and second sides of the gate structure, and said third and fourth sides of the base contact structure, whereby a strip of the main face along each said side of the gate structure and base contact structure is covered by the sidewall but other parts of the first, second and third areas of the main face remain exposed; (e) introducing atoms of the selected impurity into the substrate by way of those portions of the first, second and third areas which are exposed adjacent said sidewalls, the atoms of said selected impurity providing charge carriers of said second polarity to form heavily doped source and drain regions under the first and second areas in the MOSFET and a base region under the third area in the bipolar transistor; (f) forming a second layer of conductive material over said exposed portions of said first, second and third areas, and over the gate structure; (g) removing the conductive material of said second layer over the gate structure that is at a height over the main face that is at least as great as the height of the gate structure so as to form two discrete source and drain contacts for the MOSFET overlying said first and second areas respectively of the main face; (h) forming an emitter in the substrate under the third area for the bipolar transistor; and (i) the portion of the second conductive layer formed over the exposed third area serving as an emitter contact so that complete, operative bipolar and MOSFET devices are fabricated on a common substrate with only two layers of conductive material.

Claim 21

A method of fabricating a mixed process integrated circuit including a bipolar transistor and a metal-oxide-semiconductor field-effect transistor (MOSFET), comprising the following steps: (a) providing a substrate of semiconductor material having a main face and containing first impurity atoms that provide charge carriers of a first polarity; (b) forming and patterning a first layer of semiconductive material to provide: (i) an elongate insulated gate structure on a first portion of the main face of the substrate, first and second areas of the main face being exposed along first and second opposite sides respectively of the gate structure, said substrate having drain and source regions bounded respectively by said first and second areas of the main face and containing impurity atoms that provide charge carriers of a second polarity, opposite the first polarity, and (ii) a base contact structure on a second portion of the substrate's main face, in contact with the semiconductor material, including first and second base contact portions having opposed third and fourth sides spaced apart about a third exposed area of the main face, the substrate having a base region underlying the third area containing impurity atoms of the second polarity; (c) forming a second layer of semiconductive material in contact with the semiconductor material of the substrate over said first, second and third areas of the main face and in contact therewith and over the gate and base contact structures and insulated therefrom; (d) forming a layer of a selected material over the layer of semiconductive material, said layer of selected material having a free surface that is substantially parallel to the main face of the substrate and through which said layer of semiconductive material is exposed; and (e) anisotropically removing the semiconductive material of said second layer, but not said selected material, in a direction that is substantially perpendicular to the main face of the substrate so as to expose the gate structure and form two discrete source and drain contacts overlying said first and second areas, and a discrete emitter contact overlying said third area, respectively, of the main face whereby fabrication of operative bipolar and MOSFET devices on a common substrate can be completed with only said first and second layers of semiconductive material.

Claim 22

A method of fabricating a mixed process integrated circuit including a bipolar transistor and a metal-oxide-semiconductor field-effect transistor (MOSFET), comprising the following steps: (a) providing a substrate of semiconductor material having a main face and containing first impurity atoms that provide charge carriers of a first polarity; (b) forming and patterning a first layer of semiconductive material to provide: (i) an elongate insulated gate structure on a first portion of the main face of the substrate, first and second areas of the main face being exposed along first and second opposite sides respectively of the gate structure, said substrate having drain and source regions bounded respectively by said first and second areas of the main face and containing impurity atoms that provide charge carriers of a second polarity, opposite the first polarity, and (ii) a base contact structure on a second portion of the substrate's main face, in contact with the semiconductor material, including first and second base contact portions having opposed third and fourth sides spaced apart about a third exposed area of the main face, the substrate having a base region underlying the third area containing impurity atoms of the second polarity; (c) forming a second layer of semiconductive material in contact with the semiconductor material of the substrate over said first, second and third areas of the main face and in contact therewith and over the gate and base contact structures and insulated therefrom; (d) forming a layer of a selected material over the layer of semiconductive material, said layer of selected material having a free surface that is substantially parallel to the main face of the substrate and through which said layer of semiconductive material is exposed; and (e) anisotropically removing the semiconductive material of said second layer, but not said selected material, in a direction that is substantially perpendicular to the main face of the substrate so as to expose the gate structure and form two discrete source and drain contacts overlying said first and second areas, and a discrete emitter contact overlying said third area, respectively, of the main face whereby fabrication of operative bipolar and MOSFET devices on a common substrate can be completed with only said first and second layers of semiconductive material.

Claim 34

A method of fabricating a mixed process integrated circuit including a metal-oxide semiconductor field-effect transistor and a bipolar transistor on a common substrate, comprising the following steps, steps (f) and (g) not necessarily being in the order stated: (a) providing a substrate of semiconductor material having a main face and containing impurity atoms that provide charge carriers of a first polarity; (b) forming an elongate insulated gate structure of a predetermined height on a first portion of the substrate's main face for the metal-oxide silicon field effect transistor, and first and second areas of the main face being exposed along first and second opposite sides respectively of the gate structure; (c) forming a base contact structure on a second portion of the substrate's main face for the bipolar transistor, in contact with the semiconductor material, including first and second base contact portions having opposed third and fourth sides spaced apart about a third exposed area of the main face; (d) introducing impurity atoms that provide charge carriers of a second polarity, opposite the first polarity, into the substrate by way of said first, second and third areas of the main face, the gate structure and base contact structure being effective to mask the regions of the substrate immediately subjacent the structures from the impurity atoms; (e) forming a sidewall of a material that is opaque to atoms of a selected impurity along said first and second sides of the gate structure, and along said third and fourth sides of the base contact, whereby a strip of the main face along each said side of the gate structure and base contact structure is covered by the sidewall but other parts of the first, second and third areas of the main face remain exposed; (f) introducing atoms of the selected impurity into the substrate by way of those portions of the first, second and third areas which are exposed adjacent said sidewalls, the atoms of said selected impurity providing charge carriers of said second polarity; and (g) forming separate conductive source, drain and emitter contacts over said exposed portions of said first, second and third areas, respectively; the gate and base contact structures of steps (b) and (c) being formed simultaneously from a common first conductive layer and the conductive contacts of step (g) being formed simultaneously from a common second conductive layer.

Claim 35

A method of fabricating a mixed process integrated circuit including a metal-oxide semiconductor field-effect transistor and a bipolar transistor on a common substrate, comprising the following steps, steps (f) and (g) not necessarily being in the order stated: (a) providing a substrate of semiconductor material having a main face and containing impurity atoms that provide charge carriers of a first polarity; (b) forming an elongate insulated gate structure of a predetermined height on a first portion of the substrate's main face for the metal-oxide silicon field effect transistor, and first and second areas of the main face being exposed along first and second opposite sides respectively of the gate structure; (c) forming a base contact structure on a second portion of the substrate's main face for the bipolar transistor, in contact with the semiconductor material, including first and second base contact portions having opposed third and fourth sides spaced apart about a third exposed area of the main face; (d) introducing impurity atoms that provide charge carriers of a second polarity, opposite the first polarity, into the substrate by way of said first, second and third areas of the main face, the gate structure and base contact structure being effective to mask the regions of the substrate immediately subjacent the structures from the impurity atoms; (e) forming a sidewall of a material that is opaque to atoms of a selected impurity along said first and second sides of the gate structure, and along said third and fourth sides of the base contact, whereby a strip of the main face along each said side of the gate structure and base contact structure is covered by the sidewall but other parts of the first, second and third areas of the main face remain exposed; (f) introducing atoms of the selected impurity into the substrate by way of those portions of the first, second and third areas which are exposed adjacent said sidewalls, the atoms of said selected impurity providing charge carriers of said second polarity; and (g) forming separate conductive source, drain and emitter contacts over said exposed portions of said first, second and third areas, respectively; the gate and base contact structures of steps (b) and (c) being formed simultaneously from a common first conductive layer and the conductive contacts of step (g) being formed simultaneously from a common second conductive layer.

Claim 46

A method of fabricating a mixed process integrated circuit including a metal-oxide semiconductor field-effect transistor and a bipolar transistor on a common substrate, comprising the following steps, steps (f) and (g) not necessarily being in the order stated: (a) providing a substrate of semiconductor material having a main face and containing impurity atoms that provide charge carriers of a selected polarity; (b) forming an elongate insulated gate structure of a predetermined height on a first portion of the main face of the substrate for the metal-oxide silicon field effect transistor, and first and second areas of the main face being exposed along first and second opposite sides respectively of the gate structure; (c) forming a base contact structure on a second portion of the substrate's main face for the bipolar transistor in contact with the semiconductor material, including first and second base contact portions having opposed third and fourth sides spaced apart about a third exposed area of the main face; (d) introducing impurity atoms that provide charge carriers of a polarity opposite the selected polarity, into the substrate by way of said first, second and third areas of the main face, the gate structure and base contact structure being effective to mask the regions of the substrate immediately subjacent the structures from the impurity atoms; (e) forming a sidewall of a material that is opaque to atoms of a selected impurity along said first and second sides of the gate structure, and along said third and fourth sides of the base contact, whereby a strip of the main face along each said side of the gate structure and base contact structure is covered by the sidewall but other parts of the first, second and third areas of the main face remain exposed; (f) introducing atoms of the selected impurity into the substrate by way of those portions of the first, second and third areas which are exposed adjacent said sidewalls, the atoms of said selected impurity providing charge carriers of said opposite polarity; and (g) forming separate conductive source, drain and emitter contacts over said exposed portions of said first, second and third areas, respectively; the gate and base contact structures of steps (b) and (c) being formed simultaneously from a common first conductive layer and the conductive contacts of step (g) being formed simultaneously from a common second conductive layer.

Claim 47

A method of fabricating a mixed process integrated circuit including a metal-oxide semiconductor field-effect transistor and a bipolar transistor on a common substrate, comprising the following steps, steps (f) and (g) not necessarily being in the order stated: (a) providing a substrate of semiconductor material having a main face and containing impurity atoms that provide charge carriers of a selected polarity; (b) forming an elongate insulated gate structure of a predetermined height on a first portion of the main face of the substrate for the metal-oxide silicon field effect transistor, and first and second areas of the main face being exposed along first and second opposite sides respectively of the gate structure; (c) forming a base contact structure on a second portion of the substrate's main face for the bipolar transistor in contact with the semiconductor material, including first and second base contact portions having opposed third and fourth sides spaced apart about a third exposed area of the main face; (d) introducing impurity atoms that provide charge carriers of a polarity opposite the selected polarity, into the substrate by way of said first, second and third areas of the main face, the gate structure and base contact structure being effective to mask the regions of the substrate immediately subjacent the structures from the impurity atoms; (e) forming a sidewall of a material that is opaque to atoms of a selected impurity along said first and second sides of the gate structure, and along said third and fourth sides of the base contact, whereby a strip of the main face along each said side of the gate structure and base contact structure is covered by the sidewall but other parts of the first, second and third areas of the main face remain exposed; (f) introducing atoms of the selected impurity into the substrate by way of those portions of the first, second and third areas which are exposed adjacent said sidewalls, the atoms of said selected impurity providing charge carriers of said opposite polarity; and (g) forming separate conductive source, drain and emitter contacts over said exposed portions of said first, second and third areas, respectively; the gate and base contact structures of steps (b) and (c) being formed simultaneously from a common first conductive layer and the conductive contacts of step (g) being formed simultaneously from a common second conductive layer.