Trench gate VCMOS

Claim 2

An integrated circuit comprising: base insulative layer; a plurality of semiconductor islands on said base insulative layer separated laterally by dielectric trenches along vertical edges of said islands; a first MOS transistor in a first island having, along a first vertical edge of a first dielectric trench, drain and source regions of the same conductivity type separated by a channel region of an opposite conductivity type; a second MOS transistor in a second island separated from said first island vertically by said first trench and having, along a second vertical edge of said first dielectric trench, drain and source regions of the same conductivity type separated by a channel region of an opposite conductivity type; and a first gate in said first dielectric trench, separated from said first and second vertical edges of said first trench by gate dielectric layers and extending vertically at least across a vertical length of said channel regions, at said first and second vertical edges to form a common first gate for said first and second MOS transistors.

Claim 3

An integrated circuit according to claim 1, wherein said islands, trenches and gates have coplanar top surfaces.

Claim 4

An integrated circuit according to claim 1, wherein said gate material is doped polycrystalline semiconductor material.

Claim 5

An integrated circuit according to claim 1, wherein said drain, gate and source regions have increasing levels of impurity concentration beginning at said base insulative layer.

Claim 6

An integrated circuit according to claim 4, including first and second buried regions, in said first and second islands along said first and second vertical edges respectively on said base insulative layer, of the same conductivity type as and higher impurity concentration than a respective vertically adjacent region.

Claim 7

An integrated circuit according to claim 5, wherein said gate terminates before said first and second buried regions.

Claim 8

An integrated circuit according to claim 4, wherein said source which is at a top surface of said respective islands includes a first region of a first conductivity type at a respective vertical edge and a second region spaced from said respective vertical edges by said first region and of said first conductivity type and a higher impurity concentration than said first region.

Claim 9

An integrated circuit according to claim 1, including a third MOS transistor in said first island having drain and channel regions common to and of the same conductivity type of said drain and channel regions respectively of said first MOS transistor and a source region of the same conductivity type separate and spaced from the source region of said first MOS transistor and a third gate in said first dielectric trench separated from said first and second vertical edges by a gate dielectric layer and from said first gate by dielectric isolation and extending vertically at least across the vertical length of said channel region of said third transistor at said first vertical edge to form a third gate for said third MOS transistor.

Claim 10

An integrated circuit according to claim 1, wherein said source, channel and drain regions in said first island extend from said first vertical edge of said first trench to a third vertical edge of a second dielectric trench to form source, channel and drain regions respectively of a third MOS transistor at said third vertical edge; and a second gate in said second dielectric trench, separated from said third vertical edge of said second trench by gate dielectric and from said first gate by dielectric isolation and extending vertically at least across the vertical length of said channel region at said third vertical edge to form a second gate for said third MOS transistor.

Claim 11

An integrated circuit according to claim 9, wherein said channel and drain regions in said second island extend from said second vertical edge of said first trench to a fourth vertical edge of a third dielectric trench to form channel and source regions respectively of a fourth MOS transistor; a drain region of said fourth MOS transistor has the same conductivity type as said source region of said second MOS transistor and is at said fourth vertical edge separate and spaced from said source region of said second MOS transistor at said second vertical edge; and a third gate in said third dielectric trench separated from said fourth vertical edge of said third trench by gate dielectric and from said first and second gates by dielectric isolation and extending vertically at least across the vertical length of said channel at said fourth vertical edge to form a third gate for said fourth MOS transistor.

Claim 12

An integrated circuit comprising: base insulative layer; a plurality of semiconductor islands on said base insulative layer separated laterally by dielectric trenches along vertical edges of said islands; a first MOS transistor in a first island having, along a first vertical edge of a first dielectric trench, a first drain region of a first conductivity type, a first channel region of a second conductivity type and a first source region of said first conductivity type; a first gate in said first trench separated from said first vertical edge of said first trench by gate dielectric layer and extending vertically at least across the vertical length of said first channel region at said first vertical edge to form a first gate of said first MOS transistor; a second MOS transistor in said first island having, along a second vertical edge of a second dielectric trench a second drain region of said first conductivity type common to said first source region, a second channel region of said second conductivity type common to said first channel region and a second source region of said first conductivity type separate and spaced from said first drain region; and a second gate in said second trench separated from said second vertical edge of said second trench by gate dielectric layer and said first gate by dielectric isolation and extending vertically at least across the vertical length of said second channel region at said second vertical edge to form a second gate of said second MOS transistor.

Claim 13

An integrated circuit comprising: base insulative layer; a plurality of semiconductor islands on said base insulative layer separated laterally by dielectric trenches along vertical edges of said islands; a first MOS transistor in a first island having, along a first vertical edge of a first dielectric trench, a first drain region of a first conductivity type, a first channel region of a second conductivity type and a first source region of said first conductivity type; a first gate in said first trench separated from said first vertical edge of said first trench by gate dielectric layer and extending vertically at least across the vertical length of said first channel region at said first vertical edge to form a first gate of said first MOS transistor; a second MOS transistor in said first island having, along a second vertical edge of a second dielectric trench a second drain region of said first conductivity type common to said first source region, a second channel region of said second conductivity type common to said first channel region and a second source region of said first conductivity type separate and spaced from said first drain region; and a second gate in said second trench separated from said second vertical edge of said second trench by gate dielectric layer and said first gate by dielectric isolation and extending vertically at least across the vertical length of said second channel region at said second vertical edge to form a second gate of said second MOS transistor.

Claim 14

An integrated circuit according to claim 11, wherein said islands, trenches and gates have coplanar top surfaces.

Claim 15

An integrated circuit according to claim 11, wherein said gate material is a doped polycrystalline semiconductor material or a conductive material.

Claim 16

An integrated circuit according to claim 11, wherein said drain, gate and source regions have increasing levels of impurity concentration beginning at said base insulative layer.

Claim 17

An integrated circuit according to claim 14, including a buried region of said first conductivity type in said first island on said base insulative layer extending between said first and second vertical edges and of a higher impurity concentration than a vertically adjacent region.

Claim 18

An integrated circuit according to claim 15, wherein said first and second gates terminate before said buried layer.

Claim 19

An integrated circuit according to claim 14, wherein said source region which is at a top surface of said respective islands includes a first region of a first conductivity type at a respective vertical edge and a second region spaced from said respective vertical edges by said first region and of said first conductivity type and a higher impurity concentration than said first region.

Claim 20

An integrated circuit according to claim 11, including: a third MOS transistor in a second island having, along a third vertical edge of said first trench, third drain and third source regions of said third conductivity type separated by a channel region of a fourth conductivity type; said first gate being separated from said third vertical edge by gate dielectric layer and extending vertically at least across said third channel region at said third vertical edge to form a common first gate of said first and third MOS transistors.

Claim 21

An integrated circuit comprising: base insulative layer; a plurality of semiconductor islands on said base insulative layer separated laterally by dielectric trenches along vertical edges of said islands; an N MOS transistor in a first island having, along a first vertical edge of a first dielectric trench, N-type drain, P-type channel and N-type source regions; a P MOS transistor in a second island separated from said first island vertically by said first trench and having, along a second vertical edge of said first dielectric trench, P-type drain, N-type channel and P-type source regions; a first gate in said first dielectric trench, separated from said first and second vertical edges of said first trench by gate dielectric layers and extending vertically at least across a vertical length of said channel regions, at said first and second vertical edges to form a common first gate for said N and P MOS transistors; and said N and P MOS transistors forming an inverter having an input connected to said common first gate, drain regions of said N and P MOS transistors being connected to an output and source regions of said N and P MOS transistors being connected to first and second reference voltages respectively.

Claim 22

An integrated circuit comprising: base insulative layer; a plurality of semiconductor islands on said base insulative layer separated laterally by dielectric trenches along vertical edges of said islands; an N MOS transistor in a first island having, along a first vertical edge of a first dielectric trench, N-type drain, P-type channel and N-type source regions; a P MOS transistor in a second island separated from said first island vertically by said first trench and having, along a second vertical edge of said first dielectric trench, P-type drain, N-type channel and P-type source regions; a first gate in said first dielectric trench, separated from said first and second vertical edges of said first trench by gate dielectric layers and extending vertically at least across a vertical length of said channel regions, at said first and second vertical edges to form a common first gate for said N and P MOS transistors; and said N and P MOS transistors forming an inverter having an input connected to said common first gate, drain regions of said N and P MOS transistors being connected to an output and source regions of said N and P MOS transistors being connected to first and second reference voltages respectively.

Claim 23

An integrated circuit according to claim 19 wherein said N-type channel and P-type drain regions in said second island extend from said second vertical edge of said first trench to a third vertical edge of a third dielectric trench to form N-type channel and P-type source regions respectively of a third P MOS transistor; a P-type drain region of said third P MOS transistor is at said third vertical edge separate and spaced from said P-type source region of said P MOS transistor at said second vertical edge; and a third gate in said third dielectric trench separated from said third vertical edge of said third trench by gate dielectric and from said first and second gates by dielectric isolation and extending vertically at least across the vertical length of said channel at said third vertical edge to form a third gate for said third MOS transistor.