US6317364B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-state memory
Assignee: SanDisk Technologies LLC
•
Filing: 2000-10-13
•
Granted: 2001-11-13
•
Expires: 2020-10-13
Abstract
Abstract Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
Inventors
- 👤 Daniel C. Guterman
- 👤 Yupin Kawing Fong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:50
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C11/5642; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/06; G11C16/26; G11C16/28; G11C16/34; G11C16/3418; G11C16/3427; G11C16/349; G11C16/3495; G11C27/00; G11C27/005; G11C29/00; G11C29/70; G11C29/76; H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D30/6892; G11C16/0425; G11C2211/00; G11C2211/56; G11C2211/563; G11C2211/5634
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
75 words
A memory comprising: a plurality of EEPROM memory cells organized into a plurality of sectors, each sector including at least one wear detecting cell comprising: a read/write path; a read only path; and a floating gate shared by said read/write and said read only paths; and control circuitry for detecting the difference in conduction characteristics of said read/write and read only paths during reading, to measure the amount of wear of said wear detecting cell.
Claim 2
Dependent Claim
75 words
A memory comprising: a plurality of EEPROM memory cells organized into a plurality of sectors, each sector including at least one wear detecting cell comprising: a read/write path; a read only path; and a floating gate shared by said read/write and said read only paths; and control circuitry for detecting the difference in conduction characteristics of said read/write and read only paths during reading, to measure the amount of wear of said wear detecting cell.
Claim 3
Dependent Claim
27 words
A memory as in claim 1 which further comprises: replacement sectors for replacing those ones of said sectors having associated wear detecting cells which exhibit excessive wear.
Claim 4
Dependent Claim
29 words
A memory as in claim 1 wherein said control circuitry causes both said read/write and said read only paths to be operated during each reading of a memory cell.
Claim 5
Dependent Claim
23 words
A memory as in claim 1 wherein said control circuitry causes both said read/write and said read only paths to be periodically operated.
Claim 6
Dependent Claim
49 words
A memory as in claim 4 wherein both said read/write and said read only paths are operated based on one or more of the following events: data read failure, data read poor marginality, passage of time, number of read cycles, number of write cycles, and number of erase cycles.
Claim 7
Dependent Claim
28 words
A memory as in claim 4 wherein both said read/write and said read only paths are operated in response to a random number generator generating a predefined number.
Claim 8
Independent Claim
85 words
A method for operating a memory comprising a plurality of EEPROM memory cells organized into a plurality of sectors, each sector including at least one wear detecting cell comprising a read/write path, a read only path, and a floating gate shared by said read/write and said read only paths, said method comprising the step of: during one or more read operations, detecting the difference in conduction characteristics of said read/write and read only paths, to measure the amount of wear of said wear detecting cell.
Claim 9
Independent Claim
85 words
A method for operating a memory comprising a plurality of EEPROM memory cells organized into a plurality of sectors, each sector including at least one wear detecting cell comprising a read/write path, a read only path, and a floating gate shared by said read/write and said read only paths, said method comprising the step of: during one or more read operations, detecting the difference in conduction characteristics of said read/write and read only paths, to measure the amount of wear of said wear detecting cell.
Claim 10
Dependent Claim
28 words
A method as in claim 7 which further comprises the step of activating replacement sectors to replace those sectors having associated wear detecting cells which exhibit excessive wear.
Claim 11
Dependent Claim
18 words
A method as in claim 7 wherein both said read/write and said read only paths are periodically operated.
Claim 12
Dependent Claim
49 words
A method as in claim 9 wherein both said read/write and said read only paths are operated based on one or more of the following events: data read failure, data read poor marginality, passage of time, number of read cycles, number of write cycles, and number of erase cycles.
Claim 13
Dependent Claim
28 words
A method as in claim 9 wherein both said read/write and said read only paths are operated in response to a random number generator generating a predefined number.
References Cited (Backward Citations)
US4074304A
Cited
US4271421A
Cited
US4151020A
Cited
US4151021A
Cited
US4184207A
Cited
US4202044A
Cited
USRE32401E
Cited
US4462090A
Cited
US4302766A
Cited
US4561004A
Cited
US4331968A
Cited
US4380057A
Cited
US4803529A
Cited
US4456971A
Cited
US4488265A
Cited
US4622656A
Cited
US4821236A
Cited
US4583201A
Cited
US4575925A
Cited
US4811285A
Cited
US4616402A
Cited
US4652897A
Cited
US4663827A
Cited
JPS61181168A
Cited
US4811294A
Cited
US4862418A
Cited
US4677736A
Cited
US4805142A
Cited
US4794565A
Cited
US4943962A
Cited
JPH02360A
Cited
US4997781A
Cited
US4990979A
Cited
JPH01304784A
Cited
US5028553A
Cited
US5095344A
Cited
US5011787A
Cited
US5420060A
Cited
EP0373830A2
Cited
US5057886A
Cited
US5070032A
Cited
US5081054A
Cited
US5081056A
Cited
US5172338A
Cited
US5297148A
Cited
WO1990012400A1
Cited
US5172338B1
Cited
US5017515A
Cited
US5067108A
Cited
US5029130A
Cited
US5045488A
Cited
US5378643A
Cited
US5225361A
Cited
US5279982A
Cited
US5204841A
Cited
US5280446A
Cited
US5147816A
Cited
US5247485A
Cited
US5323355A
Cited
US5218569A
Cited
US5396468A
Cited
US5278439A
Cited
US5264384A
Cited
US5284784A
Cited
US5412600A
Cited
US5313421A
Cited
US5712180A
Cited
US5468663A
Cited
US5377147A
Cited
US5509134A
Cited
US5956742A
Cited
US5355347A
Cited
US5745475A
Cited
US5708285A
Cited
US5629890A
Cited
US5656840A
Cited
EP0725403A1
Cited
US5491657A
Cited
US5740107A
Cited
US5606521A
Cited
WO1997022123A1
Cited
US5754469A
Cited
US5818757A
Cited
US5675537A
Cited
US5771346A
Cited
US5768287A
Cited
US5867430A
Cited
US6127843A
Cited
US5894437A
Cited
US5999451A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-12 | 2005-05-14 | 2005-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-12 | 2009-05-14 | 2009-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-12 | 2013-05-14 | 2013-11-13 | $7700.00 | Window Closed / Lapsed |