US4616402A
Expired / Lapsed
US
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Method of manufacturing a semiconductor device with a stacked-gate-electrode structure
Assignee: Toshiba Corp
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Filing: 1985-05-02
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Granted: 1986-10-14
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Expires: 2005-05-02
Abstract
Abstract A method of manufacturing a semiconductor device with a stacked-gate-electrode structure which includes; forming source and drain regions in the surface portion of a semiconductor substrate in a spaced-apart relationship, forming a floating gate such that it overlies the channel region between the source and drain regions with a gate insulating film therebetween, and forming a control gate such that it overlies the floating gate with an insulating film therebetween. An oxidation-resistant film pattern having a predetermined opening is formed over a non-monocrystalline silicon layer. The non-monocrystalline silicon layer within the opening is selectively oxidized with the oxidation-resistant film pattern as a mask to form a separation insulating film. In this way, a floating gate layer is formed with the portion of the non-monocrystalline silicon layer insulatingly separated. With the oxidation-resistant film pattern left over the floating gate layer and with the separation insulating film left within the opening, a control gate layer is formed over the surface of the resultant surface to permit the whole surface of the resultant surface to be planarized.
Inventors
- 👤 Seiichi Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/156
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
188 words
A method of manufacturing a semiconductor device with a stacked-gate-electrode structure, comprising the steps of: forming an element separation area in the surface portion of a semiconductor substrate; forming a gate insulating film on an island region of said semiconductor substrate surrounded by the element separation area; forming a non-monocrystalline silicon layer on the whole surface of the resultant structure; forming over the non-monocrystalline silicon layer an oxidation-resistant film pattern having an opening at a portion thereof corresponding to a portion of the element separation area, an area of said opening being smaller than that of said portion of the element separation area; forming a first gate electrode by selectively oxidizing a non-monocrystalline silicon layer within the opening with the oxidation-resistant film pattern as a mask to form a separation insulating film with a portion of the non-monocrystalline silicon layer insulatingly separated; and forming, with said oxidation-resistant film pattern left over the first gate electrode and with said separation insulating film left within the opening, a second gate electrode over the surface of the resultant structure to permit the whole surface of the resultant structure to be planarized.
Claim 2
Independent Claim
188 words
A method of manufacturing a semiconductor device with a stacked-gate-electrode structure, comprising the steps of: forming an element separation area in the surface portion of a semiconductor substrate; forming a gate insulating film on an island region of said semiconductor substrate surrounded by the element separation area; forming a non-monocrystalline silicon layer on the whole surface of the resultant structure; forming over the non-monocrystalline silicon layer an oxidation-resistant film pattern having an opening at a portion thereof corresponding to a portion of the element separation area, an area of said opening being smaller than that of said portion of the element separation area; forming a first gate electrode by selectively oxidizing a non-monocrystalline silicon layer within the opening with the oxidation-resistant film pattern as a mask to form a separation insulating film with a portion of the non-monocrystalline silicon layer insulatingly separated; and forming, with said oxidation-resistant film pattern left over the first gate electrode and with said separation insulating film left within the opening, a second gate electrode over the surface of the resultant structure to permit the whole surface of the resultant structure to be planarized.
Claim 3
Dependent Claim
18 words
A method according to claim 1, in which said oxidation-resistant film pattern is a silicon nitride film pattern.
Claim 4
Dependent Claim
28 words
A method according to claim 1, further comprising the steps of heavily doping an impurity into the non-monocrystalline silicon layer before said non-monocrystalline silicon layer is selectively oxidized.
Claim 5
Dependent Claim
27 words
A method according to claim 3, in which phosphorus is heavily doped, as the impurity, in the order of 3×10 20 to 8×10 20 /cm 3 .
Claim 6
Dependent Claim
22 words
A method according to claim 1, in which said non-monocrystalline silicon layer is a polycrystalline silicon layer or an amorphous silicon layer.
Claim 7
Dependent Claim
25 words
A method according to claim 1, in which said second gate electrode is formed of a silicide of a metal having a high melting point.
Claim 8
Dependent Claim
18 words
A method according to claim 1, in which said second gate electrode is made of a polycide layer.
Claim 9
Dependent Claim
27 words
A method according to claim 1, in which said oxidation-resistant film pattern is formed so as to overlie said non-monocrystalline silicon layer with an insulating film therebetween.
Claim 10
Dependent Claim
18 words
A method according to claim 8, in which said oxidation-resistant film pattern is a silicon nitride film pattern.
Claim 11
Dependent Claim
28 words
A method according to claim 8, further comprising the step of heavily doping an impurity into said non-monocrystalline silicon layer before said non-monocrystalline silicon layer is selectively oxidized.
Claim 12
Dependent Claim
27 words
A method according to claim 10, in which phosphor is heavily doped, as said impurity, in the order of 3×10 20 to 8×10 20 /cm 3 .
Claim 13
Dependent Claim
22 words
A method according to claim 8, in which said non-monocrystalline silicon layer is a polycrystalline silicon layer or an amorphous silicon layer.
Claim 14
Dependent Claim
28 words
A method according to claim 8, in which said second gate electrode is formed of a metal having a high melting point or a silicide of said metal.
Claim 15
Dependent Claim
18 words
A method according to claim 8, in which said second gate electrode is formed of a polycide layer.
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