Semiconductor memory device with peripheral circuits

Claim 1

A method of manufacturing a nonvolatile semiconductor memory device comprising the steps of: forming a first semiconductive layer on a first insulating film covering a surface of a semiconductive substrate; forming a second insulating film, serving as a mask for oxidation, so as to cover said first semiconductive layer; selectively removing in a self-aligned manner portions of said second insulating film and said first semiconductive layer so as to provide a first strip of the remaining portions of the second insulating film and first semiconductive layer extending in a direction; oxidizing the surface of said substrate by using the remaining portions of the second insulating film as a mask for the oxidation so as to form a field insulator on areas of the substrate not covered with the remaining portion of the second insulating film on both sides of said strip, the field insulator being self-aligned with the strip; forming a second semiconductive layer over said second insulating film and said field insulator; selectively removing said second semiconductive layer so as to provide a second strip of the remaining portion of the second semiconductive layer extending transversely with respect to said first strip, and selectively removing portions of the first strip so as to form a floating gate of the remaining part of the first semiconductive layer self-aligned with the second strip; and introducing impurities of a conductivity type opposite to the conductivity type of the substrate into areas of the substrate not covered with the field insulator and second strip, so as to form source and drain regions self-aligned with the second strip and floating gate.

Claim 2

A method of manufacturing a nonvolatile semiconductor memory device comprising the steps of: forming a first semiconductive layer on a first insulating film covering a surface of a semiconductive substrate; forming a second insulating film, serving as a mask for oxidation, so as to cover said first semiconductive layer; selectively removing in a self-aligned manner portions of said second insulating film and said first semiconductive layer so as to provide a first strip of the remaining portions of the second insulating film and first semiconductive layer extending in a direction; oxidizing the surface of said substrate by using the remaining portions of the second insulating film as a mask for the oxidation so as to form a field insulator on areas of the substrate not covered with the remaining portion of the second insulating film on both sides of said strip, the field insulator being self-aligned with the strip; forming a second semiconductive layer over said second insulating film and said field insulator; selectively removing said second semiconductive layer so as to provide a second strip of the remaining portion of the second semiconductive layer extending transversely with respect to said first strip, and selectively removing portions of the first strip so as to form a floating gate of the remaining part of the first semiconductive layer self-aligned with the second strip; and introducing impurities of a conductivity type opposite to the conductivity type of the substrate into areas of the substrate not covered with the field insulator and second strip, so as to form source and drain regions self-aligned with the second strip and floating gate.

Claim 9

A method of manufacturing a storage transistor comprising: (a) forming a first insulating layer over a surface of a semiconductor substrate having a first conductivity type; (b) forming a first conductive layer on the first insulating layer; (c) forming a second insulating layer over the first conductive layer; (d) selectively etched said second insulating layer and first conductive layer in a self-aligned manner so that the remaining portions of the second insulating layer and first conductive layer are formed in the shape of a first strip extending in a first direction; (e) oxidizing the surface of said semiconductor substrate not having the remaining portions thereon by using the resultant second insulating layer as a mask for the oxidation so as to form a field oxide layer on areas of said surface uncovered with said first strip, whereby said field oxide layer is formed in self-alignment with said first conductive layer; (f) forming a second conductive layer over the second insulating layer of said first strip; (g) selectively etching said second conductive layer in the shape of a second strip extending in a second direction different than said first direction and serving as a control gate, and selectively etching portions of said first strip not covered by said second strip so as to form a floating gate of the remaining first conductive layer self-aligned with said second strip; and (h) introducing impurities of a conductivity type opposite to the conductivity type of the semiconductor substrate into areas of said semiconductor substrate not covered with said field oxide layer and second strip so as to form source and drain regions self-aligned with the second strip and floating gate.

Claim 10

A method of manufacturing a storage transistor comprising: (a) forming a first insulating layer over a surface of a semiconductor substrate having a first conductivity type; (b) forming a first conductive layer on the first insulating layer; (c) forming a second insulating layer over the first conductive layer; (d) selectively etched said second insulating layer and first conductive layer in a self-aligned manner so that the remaining portions of the second insulating layer and first conductive layer are formed in the shape of a first strip extending in a first direction; (e) oxidizing the surface of said semiconductor substrate not having the remaining portions thereon by using the resultant second insulating layer as a mask for the oxidation so as to form a field oxide layer on areas of said surface uncovered with said first strip, whereby said field oxide layer is formed in self-alignment with said first conductive layer; (f) forming a second conductive layer over the second insulating layer of said first strip; (g) selectively etching said second conductive layer in the shape of a second strip extending in a second direction different than said first direction and serving as a control gate, and selectively etching portions of said first strip not covered by said second strip so as to form a floating gate of the remaining first conductive layer self-aligned with said second strip; and (h) introducing impurities of a conductivity type opposite to the conductivity type of the semiconductor substrate into areas of said semiconductor substrate not covered with said field oxide layer and second strip so as to form source and drain regions self-aligned with the second strip and floating gate.

Claim 19

A method of making an electrically programmable non-volatile semiconductor memory device in the form of an array of rows and columns of memory cells comprising the steps of: applying, over a first insulating layer formed on a main surface of a semiconductor substrate, successive coatings of a first conductive layer and a second insulating layer; patterning said coatings to provide a plurality of first parallel strips, the patterned second insulating layer and first conductive layer of each first strip being self-aligned with each other; oxidizing portions of said main surface by using said patterned second insulating layer as a mask to form field oxide layers between said parallel strips, whereby the field oxide layers are formed self-aligned with said patterned first conductive layer; forming a second conductive layer over said main surface; patterning said second conductive layer to provide a plurality of second parallel strips extending transversely with respect to said first strips, and selectively removing portions of said first conductive layer of each first strip except for the remaining portions located at the intersections of said first strips and said second strips to provide a floating gate of the memory cell self-aligned with said second strip at each intersection; and introducing impurities of a conductivity type opposite to said semiconductor substrate into areas of said semiconductor substrate not covered by said field oxide layers and second strips, thereby to form source and drain regions of the memory cell self-aligned with said second strip and floating gate on both sides of each floating gate.

Claim 20

A method of making an electrically programmable non-volatile semiconductor memory device in the form of an array of rows and columns of memory cells comprising the steps of: applying, over a first insulating layer formed on a main surface of a semiconductor substrate, successive coatings of a first conductive layer and a second insulating layer; patterning said coatings to provide a plurality of first parallel strips, the patterned second insulating layer and first conductive layer of each first strip being self-aligned with each other; oxidizing portions of said main surface by using said patterned second insulating layer as a mask to form field oxide layers between said parallel strips, whereby the field oxide layers are formed self-aligned with said patterned first conductive layer; forming a second conductive layer over said main surface; patterning said second conductive layer to provide a plurality of second parallel strips extending transversely with respect to said first strips, and selectively removing portions of said first conductive layer of each first strip except for the remaining portions located at the intersections of said first strips and said second strips to provide a floating gate of the memory cell self-aligned with said second strip at each intersection; and introducing impurities of a conductivity type opposite to said semiconductor substrate into areas of said semiconductor substrate not covered by said field oxide layers and second strips, thereby to form source and drain regions of the memory cell self-aligned with said second strip and floating gate on both sides of each floating gate.