Abstract In a memory device according to the present invention, an address for writing input data into a memory (306) is designated by a first address counter (303) which operates in response to a first clock, an address for reading written data from the memory (306) is designated by a second address counter which operates in response to a second clock, and a phase difference between the outputs of the individual address counter means (303, 313) is detected by a phase comparing section (307). A timing generating section (114-116) delays a signal acquired from the first or second clock to generate three or more timings, a time difference between any two of the timings being a any non-integer multiple of the first or second clock cycle. Further, a phase comparison discriminating section (120-122, 126) latches the output of the phase comparing section (307) at three or more timings, and outputs a signal for controlling a second address counter section (313) by majority decision on the latching result.
Inventors
👤 Kazuhiko Ide
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-27 07:52
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
152 words
A memory device comprising: first address counter means operative in response to a first clock to designate an address for writing input data into a memory; second address counter means operative in response to a second clock to designate an address for reading out written data from said memory; phase comparing means for detecting a phase difference between outputs of said first and second address counter means; a timing generating means for delaying a signal acquired from said first clock or said second clock to generate three or more timings, a time difference between any two of said timings being a non-integer multiple of a cycle of said first or second clock; and phase comparison discriminating means for latching an output of said phase comparing means at said three or more timings, and outputting a signal for controlling said second address counter means by majority decision on a result of said latching.
Claim 2
Dependent Claim
152 words
A memory device comprising: first address counter means operative in response to a first clock to designate an address for writing input data into a memory; second address counter means operative in response to a second clock to designate an address for reading out written data from said memory; phase comparing means for detecting a phase difference between outputs of said first and second address counter means; a timing generating means for delaying a signal acquired from said first clock or said second clock to generate three or more timings, a time difference between any two of said timings being a non-integer multiple of a cycle of said first or second clock; and phase comparison discriminating means for latching an output of said phase comparing means at said three or more timings, and outputting a signal for controlling said second address counter means by majority decision on a result of said latching.