Method and apparatus for simultaneous address increment and memory write operations

Claim 3

The method of claim 1, and further including the step of: ceasing to apply the address signal to the memory register in response to the second transition.

Claim 4

The method of claim 1, wherein said address generator comprises a plurality of locations including a first location and a second location, said step of incrementing the write address generator comprising the step of: clocking the generator to shift a logic "1" bit from the first location to the second location.

Claim 5

The method of claim 1, wherein the step of applying the stored address signal comprises the steps of: applying an inverse of the previously stored address signal to a first input of a NOR gate having an output coupled to the memory register, in response to a second transition of a previous clock pulse; and applying the first transition to a second input of the NOR gate in order to transmit said address signal to the memory register.

Claim 8

The method of claim 5, wherein said address generator is a ring counter having first and last locations, the method including the step of: storing the address bit in a last latch in response to a positive-going transitional edge; incrementing the address bit from the last location to the first location in response to a negative-going transitional edge; and writing the stored address from the last latch to a memory register in response to the negative-going transitional edge.

Claim 9

The method of claim 5, and further comprising the step of: generating the write clock signal from leading edges of a plurality of write command pulses.

Claim 10

The method of claim 5 wherein each said respective latch is a transparent latch, the method further including the steps of: loading an address bit into a transparent latch in response to a positive-going transitional edge of the clock signal; passing an inverse of the address bit from the latch to a NOR gate in response to a successive negative-going transitional edge of the clock signal; and writing the address bit from an output of the NOR gate to a memory register in response to a negative-going transitional edge of the clock signal.

Claim 13

The method of claim 9, wherein the first transitions are negative-going and the second transitions are positive-going.

Claim 14

The method of claim 9, and further including the steps of: selecting the preselected width in order to allow the shift register to recover between first transitions; and selecting a maximum transmission frequency of the first-in first-out memory as equal to inverse of time to address memory plus recovery time of address generator.

Claim 15

Apparatus for sequentially addressing a plurality of memory registers, comprising: a clock signal source operable to transmit clock pulses, each clock pulse having first and second transitions; an address generator coupled to said clock signal source and operable to increment from a first address location to a next address location in response to said first transition of a clock pulse; storage means coupled to said generator and said clock signal source, said storage means operable to store an address signal in response to said second transition of a prior clock pulse; said address signal applied from said storage means to said memory register in response to said first transition.

Claim 16

Apparatus for sequentially addressing a plurality of memory registers, comprising: a clock signal source operable to transmit clock pulses, each clock pulse having first and second transitions; an address generator coupled to said clock signal source and operable to increment from a first address location to a next address location in response to said first transition of a clock pulse; storage means coupled to said generator and said clock signal source, said storage means operable to store an address signal in response to said second transition of a prior clock pulse; said address signal applied from said storage means to said memory register in response to said first transition.

Claim 17

The apparatus of claim 12, and further comprising: a gate coupled to an output of said storage means, said gate operable to transmit said address signal to said memory register in response to said first transition.

Claim 18

The apparatus of claim 13, wherein said gate is operable to cease transmitting said address signal in response to a next second transition occurring after said first transition.

Claim 19

The apparatus of claim 12, wherein said first transition and said second transition have opposite polarities.

Claim 20

The apparatus of claim 15, wherein the interval between said second transition and a succeeding first transition is selected to allow the recovery of the address generator between address increments, said clock signal source originating said clock pulse responsive to a leading transition of a write command pulse, the minimum interval between two of the leading transitions equal to said clock pulse plus the time necessary to allow said address generator to recover.

Claim 21

The apparatus of claim 15, wherein said first transition is negative-going and the second transition is positive-going.

Claim 22

The apparatus of claim 12, and further comprising: a plurality of address locations in said address generator including said first location, said next location and a last location; said address generator operable to increment from said first address location successively through said address locations to said last address location, said address generator next incrementing back to said first address location.

Claim 23

The apparatus of claim 12, wherein said storage means comprises a plurality of transparent latches each coupled to a respective address location.

Claim 24

The apparatus of claim 12, wherein said address generator comprises a ring counter having at one location thereof a first bit of one polarity, the remaining locations containing a second bit of the opposite polarity; said address generator operable to shift said first bit to an adjacent location responsive to said first transition.

Claim 25

The apparatus of claim 12, and further comprising a plurality of gates including said first gate, said gates each coupled to said storage means, said clock signal source and a respective memory register, a selected one of said gates receiving an inverse of said address signal from said storage means in response to said second transition, each said gate operable to transmit said address signal to a respective memory register in response to a first transition.

Claim 26

In a shift register memory system having a plurality of interconnected memory registers responsive to memory operations for writing data therein, a write controller comprising: a write clock operable to produce a plurality of write clock pulses each having a first transition and a second transition opposite to said first transition; a write address generator coupled to said clock and having a plurality of address locations, said generator responsive to said first transition to increment from a first address location to a next address location; a plurality of transparent latches coupled to said clock and associated with respective locations in said generator, each latch operable to store a write signal from a respective address location responsive to a second transition; and a plurality of gates each coupled to said clock, a respective latch, and a respective memory register, each said gate permitting the transmission of a write signal to said memory register responsive to a first transition.

Claim 27

In a shift register memory system having a plurality of interconnected memory registers responsive to memory operations for writing data therein, a write controller comprising: a write clock operable to produce a plurality of write clock pulses each having a first transition and a second transition opposite to said first transition; a write address generator coupled to said clock and having a plurality of address locations, said generator responsive to said first transition to increment from a first address location to a next address location; a plurality of transparent latches coupled to said clock and associated with respective locations in said generator, each latch operable to store a write signal from a respective address location responsive to a second transition; and a plurality of gates each coupled to said clock, a respective latch, and a respective memory register, each said gate permitting the transmission of a write signal to said memory register responsive to a first transition.

Claim 28

The write controller of claim 22, wherein each clock pulse is produced responsive to a leading transition of a write command, the width of said clock pulse determined by the amount of time necessary to write data into a memory register responsive to an address signal, the minimum interval between any two of said leading transitions equal to said clock pulse plus the time needed by said address generator to recover between increments.

Claim 29

The write controller of claim 22, wherein said first transition is negative-going and second transition is positive-going.

Claim 30

The write controller of claim 22, further comprising: a read address generator for sequentially addressing each said memory register for reading data therefrom; a comparator for comparing an address of said write address generator with an address of said read address generator to determine an equality of said addresses; read and write storage means for storing an indication of the most recent of a read or a write operation of said memory; and a preventer for preventing a memory operation of said memory registers when said comparator determines equality of said read and write addresses and when said read and write storage means has stored therein an indication that the last memory operation was a predetermined operation of said memory system.

Claim 31

The write controller of claim 22, wherein said write address generator comprises a plurality of latches each coupled to said write clock, a first address bit stored in one of said latches, a second address bit of opposite polarity to said first address bit stored in the remainder of said latches, said address generator operable to shift said first address bit to an adjacent latch in response to a first transition.

Claim 32

The write controller of claim 22, wherein each said transparent latch has an input and an output, each said transparent latch operable to produce an inverse of said write signal at said output responsive to a first transition; each said gate comprising a NOR gate operable to receive as one input thereof said write signal, said NOR gate operable to produce as its output said write signal responsive to a first transition.