Asynchronous shift register with turnpike feature

Claim 2

In an asynchronous data storage system including a source supplying data bits in sequence and an asynchronous shift register having a plurality of stages 1 . . . n connected in series with an output from stage n, each of said stages including first means for storing a data bit and a second means for producing signals indicating the full/empty status of the first means of the same stage, the improvement comprising: a plurality of input circuits, one input circuit being connected to each of said stages; and an input control means connected to said source and responsive to said second means in each of said stages for directing a data bit from said source only to the input circuit connected to the stage in said series nearest said output that is empty and has no stage preceding it which is full.

Claim 3

The improvement as claimed in claim 1 wherein said input control means comprises a plurality of gating means, there being one gating means for each of said stages, the gating means for a particular stage k in said series being connected to said source and responsive to the output signals from the second means in stage k and the second means in at least one of the stages adjacent to stage k in said series.

Claim 4

The improvement as claimed in claim 2 wherein the gating means for said particular stage k is connected to and responsive to the second means in stages k-1, k and k+1 for directing a data bit from said source to the input circuit of stage k when said second means of stages k-1, k and k+1 produce signals indicating that stages k-1 and k are empty and stage k+1 is full.

Claim 5

The improvement as claimed in claim 2 wherein the input circuit for said particular stage k is connected to the first and the second means of stage k whereby a data bit directed by the gating means for stage k is stored in said stage k first means and terminates the signal indicating the empty status of stage k.

Claim 6

In an asynchronous data storage system including a first bus for conveying zero bits and a second bus conveying one bits, and an asynchronous shift register having a plurality of stages 1 . . . n connected in series, each said stage including a zero gate, a one gate, and a full/empty status gate, the improvement comprising a gating means for each of said stages, the gating means for a particular stage k of said series comprising: a first gate having an input connected to said first bus and an output connected to the zero gate of stage k and said status gates of stage k; a second gate having an input connected to said second bus and an output connected to said one gate of stage k and said status gate of stage k; and further means connecting the outputs of the status gates of stage k and at least of the stages adjacent to stage k to the inputs of the first and second gates of stage k.

Claim 7

In an asynchronous data storage system including a first bus for conveying zero bits and a second bus conveying one bits, and an asynchronous shift register having a plurality of stages 1 . . . n connected in series, each said stage including a zero gate, a one gate, and a full/empty status gate, the improvement comprising a gating means for each of said stages, the gating means for a particular stage k of said series comprising: a first gate having an input connected to said first bus and an output connected to the zero gate of stage k and said status gates of stage k; a second gate having an input connected to said second bus and an output connected to said one gate of stage k and said status gate of stage k; and further means connecting the outputs of the status gates of stage k and at least of the stages adjacent to stage k to the inputs of the first and second gates of stage k.

Claim 8

The improvement as claimed in claim 5 wherein said further means comprises means connecting the outputs of the status gates of stages k-1, k and k+1 to the inputs of said first and second gates of stage k whereby said first or said second gate is enabled to pass a zero or a one bit, respectively when stage k+1 is full and stage k and k-1 are empty.

Claim 9

In an asynchronous data storage system including a source supplying data bits in sequence and an asynchronous shift register having a plurality of stages 1 . . . n connected in series with stage n being the output stage, each of said stages including a three state storage circuit means for producing a first output signal indicating that the stage is empty or a second output signal indicating that the stage is storing a data bit, the improvement comprising: input control means connected to said source and said three state storage circuit means in each of said stages for directing a bit of data from said source into the three stage storage circuit means in the stage nearest said output stage that is producing said first signal and has no stage preceding it wherein the three state storage circuit means is producing said second output signal.

Claim 10

In an asynchronous data storage system including a source supplying data bits in sequence and an asynchronous shift register having a plurality of stages 1 . . . n connected in series with stage n being the output stage, each of said stages including a three state storage circuit means for producing a first output signal indicating that the stage is empty or a second output signal indicating that the stage is storing a data bit, the improvement comprising: input control means connected to said source and said three state storage circuit means in each of said stages for directing a bit of data from said source into the three stage storage circuit means in the stage nearest said output stage that is producing said first signal and has no stage preceding it wherein the three state storage circuit means is producing said second output signal.