Nonvolatile integrated circuit memories having separate read/write paths

Claim 2

A nonvolatile integrated circuit memory comprising: an array of rows and columns of memory cells, each memory cell comprising a transistor having a floating gate and a control gate; a plurality of word lines, a respective one of which is connected to the respective memory cell transistors in a row of the array; a plurality of read transfer switches associated with the array, a respective one of which is connected to a respective one of the plurality of word lines of the array, to provide a read driving voltage to a selected word line of the array so that data is read from at least one selected memory cell of the array during a read operation; and a plurality of write transfer switches associated with the array, a respective one of which is also connected to a respective one of the plurality of word lines of the array, to provide a write driving voltage to a selected word line of the array so that data can be written into at least one selected memory cell of the array during a write operation; wherein said plurality of read transfer switches associated with the array comprise a plurality of first field effect transistors, and wherein said plurality of write transfer switches associated with the array comprise a plurality of second field effect transistors; wherein said plurality of first field effect transistors each includes a source and a drain, wherein only one of the source and drain includes a relatively heavily doped portion and a relatively lightly doped portion; and wherein said plurality of second field effect transistors each includes a source and a drain, wherein both the source and drain include a relatively heavily doped portion and a relatively lightly doped portion.

Claim 3

A nonvolatile integrated circuit memory according to claim 1 wherein each of said word lines of the array includes first and second ends and a central portion, and wherein a respective one of said read and write transfer switches is connected to a respective word line of the array at the central portion thereof.

Claim 4

A nonvolatile integrated circuit memory according to claim 1 wherein each of said word lines of the array includes first and second ends and a central portion, wherein a respective read transfer switch is connected to a respective word line of the array at the first end thereof, and wherein a respective write transfer switch is connected to a respective word line of the array at the second end thereof.

Claim 5

A nonvolatile integrated circuit memory according to claim 1 further comprising a read driving circuit associated with the array connected to said plurality of read transfer switches associated with the array, and a write driving circuit associated with the array connected to said plurality of write transfer switches associated with the array.

Claim 6

A nonvolatile integrated circuit memory according to claim 4 further comprising a read block selection circuit associated with the array connected to said plurality of read transfer switches associated with the array, and a write block selection circuit associated with the array connected to said plurality of write transfer switches associated with the array.

Claim 7

A nonvolatile integrated circuit memory according to claim 1 wherein said array of memory cells is divided into a plurality of memory cell strings, with the transistors in a memory cell string being serially connected to one another.

Claim 8

A nonvolatile integrated circuit memory comprising: an array of rows and columns of memory cells, each memory cell comprising a transistor having a floating gate and a control gate, said array of memory cells being divided into a plurality of memory cell strings, with the transistors in a memory cell string being serially connected; a plurality of word lines associated with the array, a respective one of which is connected to the respective memory cell transistors in a row of the array; a reading circuit associated with the array, connected to the plurality of word lines of the array, to provide a read driving voltage to the word lines so that data is read from at least one selected memory cell during a read operation; and a writing circuit associated with the array which is also connected to the plurality of word lines of the array separately from the reading circuit, to provide a write driving voltage to the word lines of the array so that data is written into at least one selected memory cell during a write operation; wherein said reading circuit associated with the array comprises a plurality of read transfer switches, a respective one of which is connected to a respective one of the plurality of word lines of the array, to provide a read driving voltage to a selected word line of the array so that data is read from at least one selected memory cell of the array during a read operation: wherein said writing circuit associated with the array comprises a plurality of write transfer switches, a respective one of which is also connected to a respective one of the plurality of word lines of the array, to provide a write driving voltage to a selected word line of the array so that data is written into at least one selected memory cell of the array during a write operation; wherein said plurality of read transfer switches associated with the array comprise a plurality of first field effect transistors, and wherein said plurality of write transfer switches associated with the array comprise a plurality of second field effect transistors; wherein said plurality of first field effect transistors each includes a source and a drain, wherein only one of the source and drain includes a relatively heavily doped portion and a relatively lightly doped portion; and wherein said plurality of second field effect transistors each includes a source and a drain,wherein both the source and drain include a relatively heavily doped portion and a relatively lightly doped portion.

Claim 9

A nonvolatile integrated circuit memory comprising: an array of rows and columns of memory cells, each memory cell comprising a transistor having a floating gate and a control gate, said array of memory cells being divided into a plurality of memory cell strings, with the transistors in a memory cell string being serially connected; a plurality of word lines associated with the array, a respective one of which is connected to the respective memory cell transistors in a row of the array; a reading circuit associated with the array, connected to the plurality of word lines of the array, to provide a read driving voltage to the word lines so that data is read from at least one selected memory cell during a read operation; and a writing circuit associated with the array which is also connected to the plurality of word lines of the array separately from the reading circuit, to provide a write driving voltage to the word lines of the array so that data is written into at least one selected memory cell during a write operation; wherein said reading circuit associated with the array comprises a plurality of read transfer switches, a respective one of which is connected to a respective one of the plurality of word lines of the array, to provide a read driving voltage to a selected word line of the array so that data is read from at least one selected memory cell of the array during a read operation: wherein said writing circuit associated with the array comprises a plurality of write transfer switches, a respective one of which is also connected to a respective one of the plurality of word lines of the array, to provide a write driving voltage to a selected word line of the array so that data is written into at least one selected memory cell of the array during a write operation; wherein said plurality of read transfer switches associated with the array comprise a plurality of first field effect transistors, and wherein said plurality of write transfer switches associated with the array comprise a plurality of second field effect transistors; wherein said plurality of first field effect transistors each includes a source and a drain, wherein only one of the source and drain includes a relatively heavily doped portion and a relatively lightly doped portion; and wherein said plurality of second field effect transistors each includes a source and a drain,wherein both the source and drain include a relatively heavily doped portion and a relatively lightly doped portion.

Claim 10

A nonvolatile integrated circuit memory according to claim 7 wherein said reading circuit further comprises a read driving circuit; and wherein said writing circuit further comprises a write driving circuit.

Claim 11

A nonvolatile integrated circuit memory according to claim 8 wherein said reading circuit further comprises a read block selection circuit; and wherein said writing circuit further comprises a write block selection circuit connected to said plurality of write transfer switches.