US5590087A
Expired / Lapsed
US
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Multi-ported data storage device with improved cell stability
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-09-25
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Granted: 1996-12-31
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Expires: 2015-09-25
Abstract
Abstract An improved memory type multi-ported data storage device is disclosed. The storage device operates to overcome the cell stability problems associated with the prior art by unidirectionally isolating memory cells of the multi-ported data storage device from read ports of the multi-ported data storage device. The unidirectional isolation operates to prevent external signals from the read ports and read port loading from influencing data stored in the memory cells, but continues to allow the memory cells to be read by the read ports associated therewith. The improved multi-ported data storage device not only allows simultaneous access to its memory cells by a large number of read ports without fear that cell stability will cause corruption of the memory cells, but also requires only a minimal amount of additional die area. Moreover, access time is independent of the number of ports being simultaneously accessed.
Inventors
- 👤 Shine Chung
- 👤 Paul G. Emerson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:51
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
417 words
A multi-ported register file, comprising: a plurality of memory cells, each of said memory cells having first and second nodes: a first plurality of write-side switching devices associated with each of said memory cells, each of said first plurality of write-side switching devices, when activated, connecting a different write bit line to the first node of said memory cell associated therewith; a second plurality of write-side switching devices associated with each of said memory cells, each of said second plurality of write-side switching devices, when activated, connecting a different write-side read bit line to the first node of said memory cell associated therewith; a plurality of read-side switching devices associated with each of said memory cells, each of said read-side switching devices, when activated, respectively connecting a different read-side read bit line to one of a plurality of read-side intermediate nodes; a plurality of unidirectional read-side isolation devices, each of said unidirectional read-side isolation devices operatively connecting the second node of one of said memory cells to one of said read-side intermediate nodes, and each of said unidirectional read-side isolation devices comprising a field-effect transistor having a gate terminal connected to the second node of one of said memory cells, a source terminal connected to a fixed voltage source and a drain terminal connected to said one of said read-side intermediate nodes, whereby each of said unidirectional read-side isolation devices substantially prevents one-of the read-side read bit lines from influencing a signal stored at one of said memory cells while enabling the signal stored at said one of said memory cells to influence said one of said read-side intermediate nodes; a plurality of unidirectional write-side isolation devices, each of said unidirectional write-side isolation devices operatively connecting the first node of one of said memory cells to one of write-side intermediate nodes, and each of said unidirectional write-side isolation devices comprising a field-effect transistor having a gate terminal connected to the first node of one of said memory cells, a source terminal connected to the fixed voltage source and a drain terminal connected to said one of said write-side intermediate nodes, whereby each of said unidirectional write-side isolation devices substantially prevents one of the write-side read bit lines from influencing a signal stored at one of said memory cells while enabling the signal stored at said one of said memory cells to influence said one of said write-side intermediate nodes; and a differential sense amplifier connected between said read-side read bit lines and said write-side read bit lines.
Claim 2
Dependent Claim
417 words
A multi-ported register file, comprising: a plurality of memory cells, each of said memory cells having first and second nodes: a first plurality of write-side switching devices associated with each of said memory cells, each of said first plurality of write-side switching devices, when activated, connecting a different write bit line to the first node of said memory cell associated therewith; a second plurality of write-side switching devices associated with each of said memory cells, each of said second plurality of write-side switching devices, when activated, connecting a different write-side read bit line to the first node of said memory cell associated therewith; a plurality of read-side switching devices associated with each of said memory cells, each of said read-side switching devices, when activated, respectively connecting a different read-side read bit line to one of a plurality of read-side intermediate nodes; a plurality of unidirectional read-side isolation devices, each of said unidirectional read-side isolation devices operatively connecting the second node of one of said memory cells to one of said read-side intermediate nodes, and each of said unidirectional read-side isolation devices comprising a field-effect transistor having a gate terminal connected to the second node of one of said memory cells, a source terminal connected to a fixed voltage source and a drain terminal connected to said one of said read-side intermediate nodes, whereby each of said unidirectional read-side isolation devices substantially prevents one-of the read-side read bit lines from influencing a signal stored at one of said memory cells while enabling the signal stored at said one of said memory cells to influence said one of said read-side intermediate nodes; a plurality of unidirectional write-side isolation devices, each of said unidirectional write-side isolation devices operatively connecting the first node of one of said memory cells to one of write-side intermediate nodes, and each of said unidirectional write-side isolation devices comprising a field-effect transistor having a gate terminal connected to the first node of one of said memory cells, a source terminal connected to the fixed voltage source and a drain terminal connected to said one of said write-side intermediate nodes, whereby each of said unidirectional write-side isolation devices substantially prevents one of the write-side read bit lines from influencing a signal stored at one of said memory cells while enabling the signal stored at said one of said memory cells to influence said one of said write-side intermediate nodes; and a differential sense amplifier connected between said read-side read bit lines and said write-side read bit lines.
Claim 3
Dependent Claim
43 words
A multi-ported register file as recited in claim 1, whereby access time to a given one of said memory cells via said read-side switching devices associated therewith is independent of the number of said read-side switching devices simultaneously accessing the given memory cell.
Claim 4
Dependent Claim
44 words
A multi-ported register file as recited in claim 1, wherein each of said first and second plurality of write-side switching devices is activated by a different write word line, and each of said read-side switching devices is activated by a different read word line.
Claim 5
Dependent Claim
23 words
A multi-ported register file as recited in claim 1, wherein each of said unidirectional read-side isolation devices consists of a single field-effect transistor.
Claim 6
Dependent Claim
16 words
A multi-ported register file as recited in claim 1, wherein the fixed voltage source is ground.
Claim 7
Dependent Claim
60 words
A multi-ported register file as recited in claim 1, wherein each of said read-side switching devices comprise a field-effect transistor having a gate terminal connected to a read word line, a drain terminal connected to a one of the read-side read bit lines and a source terminal connected to the drain terminal of said unidirectional read-side isolation device corresponding thereto.
Claim 8
Dependent Claim
73 words
The multi-ported register file of claim 1, wherein said first plurality of write-side switching devices contains at least three switching devices, said second plurality of write-side switching devices contains at least three switching devices, said plurality of read-side switching devices contains at least three switching devices, said plurality of unidirectional read-side isolation devices contains at least three isolation devices, and said plurality of unidirectional write-side isolation devices contains at least three isolation devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |