Multi-port register implementations

Claim 2

In a memory array having cells each of which is separately addressable from a plurality of write lines and is readable by a plurality of sets of bit lines, comprising: a memory cell array, a plurality of write lines coupled to each cell in the array, a plurality of sets of bit lines coupled to each cell in the array, a low order and high order word decoders coupled to each cell of the array, a low order and high order read heads coupled to each cell of the array via said plurality of bit lines, the number of said high order read heads being equal in number to the number of high order word decoders, at least one multiplexer circuit coupled to each high order read head, and an address comparison means coupled to each respective one of said high order word decoders and to each respective one of said high order read heads, said address comparison means comprising; a compare module circuit coupled to a first exclusive OR circuit, said compare module circuit comprising an exclusive-OR circuit coupled to a signal follower circuit, each of said exclusive-OR circuits being further coupled to a respective set of input address lines.

Claim 3

The memory array of claim 1 wherein said address comparison means, in the event of a compare between addresses on said set of input lines, provides a signal simultaneously to said high order word decoders and to said high order read heads to disable selected ones of said high order word decoders and inhibit selected ones of said high order read heads from reading more than one set of simultaneously addressed bit lines from the cell while switching the inhibited high order read heads to output read lines having the same address as the low order decoder.

Claim 4

The memory array of claim 1 wherein each of said sets of bit lines comprises a differential pair of bit lines, each of said read heads comprises a pair of read transistors, each of which is coupled to one of said pair of bit lines and to a differential amplifier, said differential amplifier being coupled to an output read line.

Claim 5

The memory array of claim 3 wherein each of said read heads comprise a pair of read transistors coupled to a respective bit line pair and to an output amplifier.

Claim 6

The memory array of claim 4 wherein said mutliplexer circuit comprises: means for inhibiting the bit line pair coupled to said read head, and means for transferring the input to said low order read head to the output amplifier of the read head to which the multiplexer is coupled.

Claim 7

The memory array of claim 1 wherein each of said exclusive-OR circuits comprises: a pair of cross coupled field effect transistors having their drains coupled to a respective one of address lines in said set of input address lines and their source coupled to an output line.

Claim 8

The memory array of claim 1 wherein the comparison means has its output coupled to a multiplexer circuit in a high order read head.

Claim 9

The memory array of claim 1 wherein said low order and said high order read heads are arranged serially, said low order read head being the first in said series, each high order read head being coupled to one multiplexer more than the number of multiplexers to which the preceding read head is coupled.

Claim 10

In a memory array which is separately addressable from a plurality of write lines and readable by a plurality of sets of bit lines comprising: a memory cell array, a plurality of write lines coupled to each cell in the array, a plurality of sets of bit lines coupled to each cell in the array, a plurality of word decoders coupled to each cell of the array, a plurality of read heads equal in number to the number of word decoders coupled to the cells of the array, and a multiplexer, coupled to selected ones of the high order read heads, comparator means coupled to the word decoders and each multiplexer for comparing address inputs to the word decoders and in the event of a compare disabling selected ones of the word decoders, and disabling selected ones of the high order read heads, said multiplexer switching the output data of the selected cell to output read lines having the same address as an undisabled one of said word decoders, characterized by said comparator means comprising, a first exclusive-OR circuit having a pair of cross coupled transistors having their inputs coupled to address signal inputs, and their outputs coupled to a plurality of serially connected compare module circuits, each of said compare modules comprising an exclusive-OR circuit having a pair of cross-coupled transistors having their inputs coupled to address signal inputs, and a source follower stage coupled to the output of a preceding cross-coupled exclusive-OR circuit, said follower stage of each compare module comprising first and second inverter transistors having their control electrodes coupled to the output of a preceding exclusive-OR circuit and a follower transistor having its control electrode coupled to the output of the first inverter transistor and to a voltage through a load transistor and having its output connected to an output line and to said voltage source through said second inverter transistor.

Claim 11

In a memory array which is separately addressable from a plurality of write lines and readable by a plurality of sets of bit lines comprising: a memory cell array, a plurality of write lines coupled to each cell in the array, a plurality of sets of bit lines coupled to each cell in the array, a plurality of word decoders coupled to each cell of the array, a plurality of read heads equal in number to the number of word decoders coupled to the cells of the array, and a multiplexer, coupled to selected ones of the high order read heads, comparator means coupled to the word decoders and each multiplexer for comparing address inputs to the word decoders and in the event of a compare disabling selected ones of the word decoders, and disabling selected ones of the high order read heads, said multiplexer switching the output data of the selected cell to output read lines having the same address as an undisabled one of said word decoders, characterized by said comparator means comprising, a first exclusive-OR circuit having a pair of cross coupled transistors having their inputs coupled to address signal inputs, and their outputs coupled to a plurality of serially connected compare module circuits, each of said compare modules comprising an exclusive-OR circuit having a pair of cross-coupled transistors having their inputs coupled to address signal inputs, and a source follower stage coupled to the output of a preceding cross-coupled exclusive-OR circuit, said follower stage of each compare module comprising first and second inverter transistors having their control electrodes coupled to the output of a preceding exclusive-OR circuit and a follower transistor having its control electrode coupled to the output of the first inverter transistor and to a voltage through a load transistor and having its output connected to an output line and to said voltage source through said second inverter transistor.

Claim 12

An address comparison circuit comprising: an input stage, and a compare module circuit coupled to an output line, said input stage being an exclusive-OR circuit coupled to said module circuit, said compare module circuit comprising an exclusive-OR circuit coupled to a signal follower circuit, each of said exclusive-OR circuits being coupled to input address lines.

Claim 13

An address comparison circuit comprising: an input stage, and a compare module circuit coupled to an output line, said input stage being an exclusive-OR circuit coupled to said module circuit, said compare module circuit comprising an exclusive-OR circuit coupled to a signal follower circuit, each of said exclusive-OR circuits being coupled to input address lines.

Claim 14

The comparison circuit of claim 10 wherein each of said exclusive-OR circuits comprises: a pair of cross coupled field effect transistors having their drains coupled to respective input address lines.

Claim 15

A comparator comprising: an input stage having an output coupled to a compare module circuit having an input and an output, said input stage being an exclusive-OR circuit coupled to the input of said compare module, said compare module comprising an exclusive-OR circuit having a pair of cross-coupled transistors having their inputs coupled to address signal inputs and a source follower stage coupled to the output of the input stage and to the output of the compare module circuit, said follower stage comprising first and second inverter transistors having their control electrodes coupled to the output of the input stage and a follower transistor having its control electrode coupled to the output of the first inverter transistor and to a voltage through a load transistor and having its output connected to the output of the compare module circuit and to said voltage source through said second inverter transistor.

Claim 16

A comparator comprising: an input stage having an output coupled to a compare module circuit having an input and an output, said input stage being an exclusive-OR circuit coupled to the input of said compare module, said compare module comprising an exclusive-OR circuit having a pair of cross-coupled transistors having their inputs coupled to address signal inputs and a source follower stage coupled to the output of the input stage and to the output of the compare module circuit, said follower stage comprising first and second inverter transistors having their control electrodes coupled to the output of the input stage and a follower transistor having its control electrode coupled to the output of the first inverter transistor and to a voltage through a load transistor and having its output connected to the output of the compare module circuit and to said voltage source through said second inverter transistor.

Claim 17

The comparator of claim 12 wherein another compare module circuit is serially coupled to the output of the compare module coupled to the input stage.

Claim 18

A comparator circuit comprising: an input stage, and a plurality of compare module circuits serially coupled to said input stage, said input stage being an exclusive-OR circuit coupled to the input of the first of said serially coupled compare module circuits, each of said compare module circuits comprising an exlcusive-OR circuit coupled to a source follower circuit, each of said exclusive-OR circuits being coupled to input address lines.

Claim 19

A comparator circuit comprising: an input stage, and a plurality of compare module circuits serially coupled to said input stage, said input stage being an exclusive-OR circuit coupled to the input of the first of said serially coupled compare module circuits, each of said compare module circuits comprising an exlcusive-OR circuit coupled to a source follower circuit, each of said exclusive-OR circuits being coupled to input address lines.