Write suppression in bipolar transistor memory cells

Claim 2

A bistable storage cell comprised of semiconductor transistors for storing data representative of binary information and having an input connection to the cell and an output connection from the cell, said semiconductor transistors capable of being driven into saturation; logic means connected to said cell and responsive to the binary state of said cell, said logic means including an exclusive OR circuit; means connected to said cell for writing said data into said cell, said logic means inhibiting the writing of information into said cell when said cell state and the data to be written are representative of the same binary information, and including means in said logic means to immediately inhibit further writing into said cell upon said cell switching states whereby further saturation of said cell is prevented.

Claim 3

A bistable storage cell comprised of bipolar transistors for storing data representative of binary information said bipolar transistors being capable of being driven into saturation; logic means connected to said cell and responsive to the binary state of said cell, said logic means including an exclusive OR circuit; and means in said logic means to inhibit the writing of data into said cell when said cell state and the data to be written are representative of the same binary information, and means in said logic means to inhibit further writing of data into said cell when said cell switches states whereby further saturation of said cell is prevented.

Claim 4

A bistable storage cell comprised of bipolar transistors for storing data representative of binary information said bipolar transistors being capable of being driven into saturation; logic means connected to said cell and responsive to the binary state of said cell, said logic means including an exclusive OR circuit; and means in said logic means to inhibit the writing of data into said cell when said cell state and the data to be written are representative of the same binary information, and means in said logic means to inhibit further writing of data into said cell when said cell switches states whereby further saturation of said cell is prevented.

Claim 5

A circuit for write suppression in at least one monolithic semiconductor storage cell in which storage is accomplished in a bistable environment; said storage cell including an input and an output, read amplifier means connected to said output, and data output means connected to said read amplifier means; gating and comparing means responsive to the output signal of said cell and to a signal to be written into said cell; means for feeding said signal at the output of said cell into said gating and comparing means, said gating and comparing means including an exclusive OR circuit, said gating and comparing means gating said signal to be written into said cell when said output signal and said signal to be written into said cell differ, and inhibiting the writing in of said signal when said signals are the same whereby further saturation of said semiconductor storage cell is prevented.

Claim 6

A circuit for write suppression in at least one monolithic semiconductor storage cell in which storage is accomplished in a bistable environment; said storage cell including an input and an output, read amplifier means connected to said output, and data output means connected to said read amplifier means; gating and comparing means responsive to the output signal of said cell and to a signal to be written into said cell; means for feeding said signal at the output of said cell into said gating and comparing means, said gating and comparing means including an exclusive OR circuit, said gating and comparing means gating said signal to be written into said cell when said output signal and said signal to be written into said cell differ, and inhibiting the writing in of said signal when said signals are the same whereby further saturation of said semiconductor storage cell is prevented.

Claim 7

A circuit for write suppression in accordance with claim 1 including means for applying a write instruction to said gating and comparing means whereby said gating and comparing means is able to receive said signal to be written and said output signal.

Claim 8

A circuit for write suppression in accordance with claim 4 including a write amplifier, means connecting said write amplifier to said gating and comparing means, and means for applying said input signal to said write amplifier.

Claim 9

A circuit for write suppression in at least one monolithic semiconductor storage cell in which storage is accomplished in a bistable environment, said storage cell including an input and an output, and comprising a pair of double-emitter bipolar transistors, said input being connected to one emitter of each of said pair of transistors, and said output being connected to the emitters of a pair of read transistors whose bases are coupled to respective bases of said double emitter transistors; gating and comparing means responsive to the output signal of said cell and to a signal to be written into said cell; said gating and comparing means comprising a pair of emitter follower transistors coupled through the emitters each to one junction of a pair of diodes, and means coupling the other junction of said diodes to the input of said storage cell; said gating and comparing means gating said signal to be written into said cell when said output signal and said signal to be written into said cell differ, and inhibiting the writing in of said signal when said signals are the same whereby further saturation of said storage cell is prevented.

Claim 10

A circuit for write suppression in at least one monolithic semiconductor storage cell in which storage is accomplished in a bistable environment, said storage cell including an input and an output, and comprising a pair of double-emitter bipolar transistors, said input being connected to one emitter of each of said pair of transistors, and said output being connected to the emitters of a pair of read transistors whose bases are coupled to respective bases of said double emitter transistors; gating and comparing means responsive to the output signal of said cell and to a signal to be written into said cell; said gating and comparing means comprising a pair of emitter follower transistors coupled through the emitters each to one junction of a pair of diodes, and means coupling the other junction of said diodes to the input of said storage cell; said gating and comparing means gating said signal to be written into said cell when said output signal and said signal to be written into said cell differ, and inhibiting the writing in of said signal when said signals are the same whereby further saturation of said storage cell is prevented.

Claim 11

A circuit for write suppression in accordance with claim 6 wherein said diodes comprise transistors having their base and collectors shorted together, said means coupling said storage cell to said diodes being connected to the emitters of said diode connected transistors.

Claim 12

A circuit for write suppression in accordance with claim 7 wherein said storage cell output is connected to said one junction of said diodes.

Claim 13

A circuit for write suppression in accordance with claim 8 including a pair of emitter follower transistors connected to said storage cell output and said one junction of said diodes, intermediate said cell output and said one junction of said diodes.

Claim 14

A circuit for write suppression in accordance with claim 9 including a read amplifier intermediate said emitter follower transistors and said storage cell.