Nondestructive read transistor memory cell

Claim 1

A MEMORY CELL HAVING TWO STABLE STATES REPRESENTED BY SELECTIVE CONDUCTION OF A TRIGGER PAIR OF TRANSISTORS COMPRISING A FIRST AND A SECOND TRIGGER TRANSISTOR EACH HAVING AN EMITTER, BASE AND COLLECTOR; MEANS FOR DIRECCTLY CROSS-COUPLING THE COLLECTORS AND THE BASES OF SAID TRANSISTORS; A FIRST AND A SECOND DIODE COUPLED TO THE EMITTER OF EACH OF SAID TRANSISTORS; A CONTROL TERMINAL MEANS FOR COUPLING SAID SECOND DIODES TO SAID CONTROL TERMINAL; READ CONTROL MEANS COMPRISING A FIRST AND A SECOND TRANSISTOR COUPLED TO EACH OF SAID FIRST DIODES; MEANS FOR APPLYING A CONTROL PULSE TO SAID CONTROL TERMINAL; MEANS FOR APPLYING A READ-IN SIGNAL TO ONE OF SAID FIRST READ CONTROL TRANSISTORS COINCIDENT WITH THE PRESENCE OF SAID CONTROL SIGNAL WHEREBY THE CORRESPONDING TRIGGER TRANSISTOR IS ACTUATED TO A CONDUCTING STATE THROUGH THE CORRESPONDNG FIRST DIODE TO SET THE MEMORY CELL TO THE CORRESPONDING STATE; AND MEANS FOR THEN APPLYING A CONTROL PULSE TO SAID CONTROL TERMINAL WHEREBY THE TATE OF THE MEMORY CELL IS NONDESTRUCTIVELY READ OUT TO THE CORRESPONDING SECOND READ CONTROL TRANSISTOR.