US5147816A
Expired / Lapsed
US
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Method of making nonvolatile memory array having cells with two tunelling windows
Assignee: Texas Instruments Inc
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Filing: 1991-07-26
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Granted: 1992-09-15
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Expires: 2011-07-26
Abstract
Abstract A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first, second and third sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned over and insulated from the floating gates of the cells for reading, programming and erasing the cells. The row lines, including control gates, are also positioned over and insulated from the third sub-channels. The field-plate conductor permits programming of the cells through the first tunnelling window only and erasing of the cells through the second tunnelling window only, or vice versa.
Inventors
- 👤 Manzur Gill
- 👤 Theodore D. Lindgren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:33
CPC Classifications
H; H10; H10B; H10B69/00; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
305 words
A method for fabricating a nonvolatile memory array at a face of a semiconductor layer of a first conductivity-type, comprising: selectively doping said semiconductor layer with a dopant of a second conductivity-type opposite said first conductivity-type to create pairs of source-column lines and drain-column lines, each said drain-column line in a pair spaced from each said source-column line in said pair by first, second and third sub-channels, said first sub-channel adjacent said drain-column line, said second sub-channel adjacent said source-column line; differentially growing a first thermal insulator region over each said source-column line and a second thermal insulator region over each said drain-column line; forming first and second tunnelling windows, each said first tunnelling window formed on an edge of said source-column line opposite said second sub-channel, each said second tunnelling window formed on an edge of said drain-column line opposite said first sub-channel; forming a first conductive layer and a first insulator layer over said face, said first conductive layer insulated from said sub-channels; selectively forming a second insulator layer over said first insulator layer; selectively etching said first conductive layer, said first insulator layer and said second insulator layer to define field-plate lines, field-plate insulators, floating-gate strips and inter-level-insulator strips, each said field-plate line and each said field plate insulator formed over at least a part of said second thermal insulator region and over said first sub-channel of a said pair, each said floating-gate strip and each said inter-level-insulator strip formed over at least said first thermal insulator region, over said second sub-channel of said pair, over said first tunnelling window of said pair, and over said second tunnelling window of an adjacent said pair; forming a row-line/control-gate layer insulated from said floating-gate strips and from said third sub-channels; forming row-lines/control-gates and floating gates from said row-line/control-gate layer and from said floating-gate strips.
Claim 2
Independent Claim
305 words
A method for fabricating a nonvolatile memory array at a face of a semiconductor layer of a first conductivity-type, comprising: selectively doping said semiconductor layer with a dopant of a second conductivity-type opposite said first conductivity-type to create pairs of source-column lines and drain-column lines, each said drain-column line in a pair spaced from each said source-column line in said pair by first, second and third sub-channels, said first sub-channel adjacent said drain-column line, said second sub-channel adjacent said source-column line; differentially growing a first thermal insulator region over each said source-column line and a second thermal insulator region over each said drain-column line; forming first and second tunnelling windows, each said first tunnelling window formed on an edge of said source-column line opposite said second sub-channel, each said second tunnelling window formed on an edge of said drain-column line opposite said first sub-channel; forming a first conductive layer and a first insulator layer over said face, said first conductive layer insulated from said sub-channels; selectively forming a second insulator layer over said first insulator layer; selectively etching said first conductive layer, said first insulator layer and said second insulator layer to define field-plate lines, field-plate insulators, floating-gate strips and inter-level-insulator strips, each said field-plate line and each said field plate insulator formed over at least a part of said second thermal insulator region and over said first sub-channel of a said pair, each said floating-gate strip and each said inter-level-insulator strip formed over at least said first thermal insulator region, over said second sub-channel of said pair, over said first tunnelling window of said pair, and over said second tunnelling window of an adjacent said pair; forming a row-line/control-gate layer insulated from said floating-gate strips and from said third sub-channels; forming row-lines/control-gates and floating gates from said row-line/control-gate layer and from said floating-gate strips.
Claim 3
Dependent Claim
15 words
The method of claim 1, including: forming an oxide-nitride-oxide layer on said first conductive layer.
Claim 4
Dependent Claim
15 words
The method of claim 1, including: implanting dopant through said first and second tunnelling windows.
Claim 5
Independent Claim
322 words
A method for fabricating a nonvolatile memory array at a face of a semiconductor layer of a first conductivity type, comprising: selectively doping said semiconductor layer with a dopant of a second conductivity-type opposite said first conductivity-type to create pairs of source-column lines and drain-column lines, each said drain-column line of said pair spaced from each said source-column line of said pair by first, second and third sub-channels, said first sub-channel adjacent said drain-column line of said pair, said second sub-channel adjacent said source-column line of said pair; differentially growing a first thermal insulator region over each said source-column line and a second thermal insulator region over each said drain-column line; forming a first conductive layer and a first insulator layer over said face, said first conductive layer insulated from said sub-channels; selectively etching said first conductive layer and said first insulator layer to define field-plate lines and field-plate insulators, each said field-plate line and each said field plate insulator formed over at least a part of a said second thermal insulator region and over at least said first sub-channel of said pair; forming first and second tunnelling windows, each said first tunnelling window formed over said source-column line of said pair on an edge of said source-column line opposite said second sub-channel, each said second tunnelling window formed over said drain column line of said pair on an edge of said drain-column line opposite said first sub-channel; forming floating-gate strips over said face, each said floating-strip over at least one said first tunnelling window of said pair and over at least one said second tunnelling window of an adjacent said pair, said second sub-channel of said pair under and insulated from one of said floating-gate strips; forming a row-line/control-gate layer insulated from said floating-gate strips; forming row-lines/control-gates and floating gates from said row-line/control-gate layer and from said floating-gate strips, said third sub-channel of said pair under one of said row-line/control gates.
Claim 6
Independent Claim
322 words
A method for fabricating a nonvolatile memory array at a face of a semiconductor layer of a first conductivity type, comprising: selectively doping said semiconductor layer with a dopant of a second conductivity-type opposite said first conductivity-type to create pairs of source-column lines and drain-column lines, each said drain-column line of said pair spaced from each said source-column line of said pair by first, second and third sub-channels, said first sub-channel adjacent said drain-column line of said pair, said second sub-channel adjacent said source-column line of said pair; differentially growing a first thermal insulator region over each said source-column line and a second thermal insulator region over each said drain-column line; forming a first conductive layer and a first insulator layer over said face, said first conductive layer insulated from said sub-channels; selectively etching said first conductive layer and said first insulator layer to define field-plate lines and field-plate insulators, each said field-plate line and each said field plate insulator formed over at least a part of a said second thermal insulator region and over at least said first sub-channel of said pair; forming first and second tunnelling windows, each said first tunnelling window formed over said source-column line of said pair on an edge of said source-column line opposite said second sub-channel, each said second tunnelling window formed over said drain column line of said pair on an edge of said drain-column line opposite said first sub-channel; forming floating-gate strips over said face, each said floating-strip over at least one said first tunnelling window of said pair and over at least one said second tunnelling window of an adjacent said pair, said second sub-channel of said pair under and insulated from one of said floating-gate strips; forming a row-line/control-gate layer insulated from said floating-gate strips; forming row-lines/control-gates and floating gates from said row-line/control-gate layer and from said floating-gate strips, said third sub-channel of said pair under one of said row-line/control gates.
Claim 7
Dependent Claim
14 words
The method of claim 4, including: forming an oxide-nitride-oxide layer on said floating-gate strips.
Claim 8
Dependent Claim
15 words
The method of claim 4, including: implanting dopant through said first and second tunnelling windows.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |