US4994403A
Expired / Lapsed
US
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Method of making an electrically programmable, electrically erasable memory array cell
Assignee: Texas Instruments Inc
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Filing: 1989-12-28
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Granted: 1991-02-19
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Expires: 2009-12-28
Abstract
Abstract A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective drain regions (30a, 30b), a shared source region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) which may be programmed by hot electron injection and erased by Fowler-Nordheim electron tunneling through respective tunneling oxide windows (40a, 40b) overlying a portion of source region (28) adjacent respective channels (38a, 38b). A wordline or control gate conductor (62) is insulatively disposed adjacent the floating gates (46a, 46b) to program or erase.
Inventors
- 👤 Manzur Gill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:43
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
213 words
A method for fabricating at least first and second electrically erasable and programmable memory cells at a face of a semiconductor layer having a first conductivity type, comprising the steps of: selectively doping the semiconductor layer with a dopant of a second conductivity type opposite the first conductivity type to create a drain region of the first cell, a shared source region spaced from the drain region of the first cell by a channel region of the first cell, and a drain region of the second cell spaced from the source region by a channel region of the second cell; differentially growing an insulator layer over the face to create thick insulator regions over the source and drain regions, and a relatively thin insulator layer in between the source region and the drain regions; selectively removing the thin insulator layer to expose first and second window areas on the source region adjacent the channel regions of the respective first and second cells; forming a first conductive layer over the face; selectively etching the first conductive layer to define first and second floating gate conductors, each formed over a respective thin window insulator and the channel adjacent the respective thin window insulator; and forming a control gate conductor insulatively adjacent the floating gate conductors.
Claim 2
Independent Claim
213 words
A method for fabricating at least first and second electrically erasable and programmable memory cells at a face of a semiconductor layer having a first conductivity type, comprising the steps of: selectively doping the semiconductor layer with a dopant of a second conductivity type opposite the first conductivity type to create a drain region of the first cell, a shared source region spaced from the drain region of the first cell by a channel region of the first cell, and a drain region of the second cell spaced from the source region by a channel region of the second cell; differentially growing an insulator layer over the face to create thick insulator regions over the source and drain regions, and a relatively thin insulator layer in between the source region and the drain regions; selectively removing the thin insulator layer to expose first and second window areas on the source region adjacent the channel regions of the respective first and second cells; forming a first conductive layer over the face; selectively etching the first conductive layer to define first and second floating gate conductors, each formed over a respective thin window insulator and the channel adjacent the respective thin window insulator; and forming a control gate conductor insulatively adjacent the floating gate conductors.
Claim 3
Dependent Claim
56 words
The method of claim 1, and further comprising the steps of: after said step of forming the first conductive layer over the face, forming an oxide layer on the first conductive layer; forming a nitride layer on the oxide layer; and forming a second oxide layer on the nitride layer to create a three-insulator oxide-nitride-oxide layer.
Claim 4
Dependent Claim
126 words
The method of claim 1, wherein the first and second cells are formed within an array of such cells formed in parallel rows and columns formed at an angle to the rows, the method further comprising: selectively etching the first conductive layer to form spaced apart columnar strips, each group of two adjacent strips including first and second floating gate conductor strips; forming a second conductive layer over the face; and etching the second conductive layer and the floating gate conductor strips to define a control gate conductor for each row that is elongate in a row direction and a plurality of floating gate conductors having edges in a row direction that are aligned with the edges in the row direction of respective control gate conductors.
Claim 5
Dependent Claim
62 words
The method of claim 3, and further comprising the steps of: during the step of etching the second conductive layer and the floating gate conductor strips, exposing regions of the semiconductor layer; doping the exposed regions with a dopant of a first conductivity type to form doped regions in the semiconductor layer; and forming a thick oxide layer over the doped regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |