US4892840A
Expired / Lapsed
US
⏱️ 0.0 years remaining
EPROM with increased floating gate/control gate coupling
Assignee: Texas Instruments Inc
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Filing: 1989-04-11
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Granted: 1990-01-09
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Expires: 2009-04-11
Abstract
Abstract Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.
Inventors
- 👤 Agerico L. Esquivel
- 👤 Robert Groover, III
- 👤 Howard L. Tigelaar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:36
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/014; H10W10/10; H10W10/13; H10W10/17
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
170 words
A method for fabricating a non-volatile memory array, comprising the steps of: forming a plurality of bit line diffusions overlaid by bit line insulators near the surface of a semiconductor body to define channel regions in said semiconductor body located between said bit line diffusions; etching away portions of said semiconductor body on opposing sides of said channel regions to define trenches having a depth at least half that of said bit line diffusion; filling said trenches with a dielectric; depositing over said semiconductor body and patterning a first insulated conductive layer to form conductive strips; depositing over said first insulated conductive layer a second insulated conducting layer; and etching said second conductive layer to form word lines which are not parallel to said bit line diffusions, while also etching away portions of said first conductive layer which do not underlie portions of said second conductive layer, and etching said first and second layers in a pattern so that at least a portion of said layers overlie said dielectric-filled trenches.
Claim 2
Independent Claim
170 words
A method for fabricating a non-volatile memory array, comprising the steps of: forming a plurality of bit line diffusions overlaid by bit line insulators near the surface of a semiconductor body to define channel regions in said semiconductor body located between said bit line diffusions; etching away portions of said semiconductor body on opposing sides of said channel regions to define trenches having a depth at least half that of said bit line diffusion; filling said trenches with a dielectric; depositing over said semiconductor body and patterning a first insulated conductive layer to form conductive strips; depositing over said first insulated conductive layer a second insulated conducting layer; and etching said second conductive layer to form word lines which are not parallel to said bit line diffusions, while also etching away portions of said first conductive layer which do not underlie portions of said second conductive layer, and etching said first and second layers in a pattern so that at least a portion of said layers overlie said dielectric-filled trenches.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein said first conductive layer is not crystalline and comprises at least 30% atomic of silicon.
Claim 4
Dependent Claim
21 words
The method of claim 1, wherein said second conductive layer is not crystalline and comprises at least 30% atomic of silicon.
Claim 5
Dependent Claim
21 words
The method of claim 1, wherein said second conductive layer is polycrystalline and comprises a substantial fraction of a metal silicide.
Claim 6
Dependent Claim
17 words
The method of claim 1, further comprising oxidizing sidewalls of said trench to form a passivating layer.
Claim 7
Dependent Claim
21 words
The method of claim 1, further including implanting an additional dose of a dopant impurity into the bottom of said trench.
Claim 8
Dependent Claim
27 words
The method of claim 1, wherein said step of depositing a first insulated conductive layer comprises a preliminary substep of growing a dielectric on said semiconductor body.
Claim 9
Dependent Claim
30 words
The method of claim 1 , wherein said step of depositing a second insulated conductive layer comprises a preliminary substep of depositing a dielectric on said first insulated conductive layer.
Claim 10
Independent Claim
143 words
A method for fabricating a non-volatile memory array, comprising the steps of: forming a plurality of bit line diffusions near the surface of a semiconductor body to define channel regions therebetween; etching away portions of said semiconductor body to define individual channel regions located between said bit lines, and filling said etched portions with a dielectric; planarizing the top surface of said dielectric; depositing on said semiconductor body and over said dielectric-filled etched portions a first insulated conductive layer; etching said first insulated conductive layer to form conductive strips; depositing on said first insulated conductive layer a second insulated conductive layer; and etching said second conductive layer to form word lines which are not parallel to said bit line diffusions, while also etching away portions of said first conductive layer leaving portions of said first and second layers overlying said dielectric-filled etched portions.
Claim 11
Independent Claim
143 words
A method for fabricating a non-volatile memory array, comprising the steps of: forming a plurality of bit line diffusions near the surface of a semiconductor body to define channel regions therebetween; etching away portions of said semiconductor body to define individual channel regions located between said bit lines, and filling said etched portions with a dielectric; planarizing the top surface of said dielectric; depositing on said semiconductor body and over said dielectric-filled etched portions a first insulated conductive layer; etching said first insulated conductive layer to form conductive strips; depositing on said first insulated conductive layer a second insulated conductive layer; and etching said second conductive layer to form word lines which are not parallel to said bit line diffusions, while also etching away portions of said first conductive layer leaving portions of said first and second layers overlying said dielectric-filled etched portions.
Claim 12
Dependent Claim
21 words
The method of claim 9, wherein said first conductive layer is not crystalline and comprises at least 30% atomic of silicon.
Claim 13
Dependent Claim
21 words
The method of claim 9, wherein said second conductive layer is not crystalline and comprises at least 30% atomic of silicon.
Claim 14
Dependent Claim
21 words
The method of claim 9, wherein said second conductive layer is polycrystalline and comprises a substantial fraction of a metal silicide.
Claim 15
Dependent Claim
20 words
The method of claim 9, further comprising the step of oxidizing sidewalls of said trench to form a passivating layer.
Claim 16
Dependent Claim
25 words
The method of claim 9, further comprising the step of implanting an additional dose of a dopant impurity into the bottom of said etched portion.
Claim 17
Dependent Claim
27 words
The method of claim 9, wherein said step of depositing a first insulated conductive layer comprises a preliminary substep of growing a dielectric on said semiconductor body.
Claim 18
Dependent Claim
29 words
The method of claim 9, wherein said step of depositing a second insulated conductive layer comprises a preliminary substep of depositing a dielectric on said first insulated conductive layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-08 | 1993-07-10 | 1994-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-08 | 1997-07-10 | 1998-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-08 | 2001-07-10 | 2002-01-09 | $7700.00 | Window Closed / Lapsed |