US4372031A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making high density memory cells with improved metal-to-silicon contacts
Assignee: Texas Instruments Inc
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Filing: 1980-03-21
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Granted: 1983-02-08
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Expires: 2000-03-21
Abstract
Abstract Semiconductor read only memory (ROM) or electrically programmable memory (EPROM) devices are constructed using a metal-to-silicon contact arrangement which provides small cell size. An intervening polysilicon segment allows the silicon region underlying a metal contact area to be much smaller than in prior cells. The layout and cell structure provides a high density array. The use of the polysilicon segment also prevents the occurance of problems with spiking of metal through shallow implanted N+ regions.
Inventors
- 👤 Shyh-Chang Tsaur
- 👤 Chang-Kiang Kuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:51
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
205 words
A method of making an array of memory cells in a face of a semiconductor body, each memory cell including an insulated gate field-effect transistor having a gate electrode and a source/drain path between source and drain regions; comprising the steps of: applying a first layer of conductive material to said face and patterning such layer to define said gate electrode of each of a plurality of said cells, introducing conductivity-type determining impurity into said face adjacent said gate electrodes to define said source and drain regions of each of said cells, applying a second layer of conductive material to said face insulated from said first layer and patterning it to define a connector segment which contacts said source or drain regions at a first contact area for each adjacent set of said cells, each connector segment extending across at least one of said first electrodes, and applying a metal layer to said face insulated from the first and second layers except at second contact areas and patterning the metal layer to define a plurality of lines each of which extends across a plurality of adjacent sets of cells, the second contact areas being parts of said connector segment spaced from said first contact areas.
Claim 2
Independent Claim
205 words
A method of making an array of memory cells in a face of a semiconductor body, each memory cell including an insulated gate field-effect transistor having a gate electrode and a source/drain path between source and drain regions; comprising the steps of: applying a first layer of conductive material to said face and patterning such layer to define said gate electrode of each of a plurality of said cells, introducing conductivity-type determining impurity into said face adjacent said gate electrodes to define said source and drain regions of each of said cells, applying a second layer of conductive material to said face insulated from said first layer and patterning it to define a connector segment which contacts said source or drain regions at a first contact area for each adjacent set of said cells, each connector segment extending across at least one of said first electrodes, and applying a metal layer to said face insulated from the first and second layers except at second contact areas and patterning the metal layer to define a plurality of lines each of which extends across a plurality of adjacent sets of cells, the second contact areas being parts of said connector segment spaced from said first contact areas.
Claim 3
Dependent Claim
19 words
A method according to claim 1 wherein the semiconductor body is silicon, and the conductive material is polycrystalline silicon.
Claim 4
Dependent Claim
26 words
A method according to claim 2 wherein the first layer is patterned to define first elongated strips defining address lines before the second layer is applied.
Claim 5
Dependent Claim
22 words
A method according to claim 3 wherein the first layer defines the gates of a plurality of field effect transistors in rows.
Claim 6
Dependent Claim
24 words
A method according to claim 4 wherein a thick insulator separates said layer of metal from said face except at said second contact area.
Claim 7
Dependent Claim
27 words
A method according to claim 5 wherein a coating of thick thermal field oxide is formed on parts of said face before applying said first conductive layer.
Claim 8
Dependent Claim
41 words
A method according to claim 6 wherein an array of rows and columns of said cells is formed at said face, and the layer of metal includes parallel strips of metal, each strip contacting a plurality of cells in a column.
Claim 9
Dependent Claim
25 words
A method according to claim 7 wherein each connector segment includes wide areas at said second contact areas alternately spaced along adjacent columns of cells.
Claim 10
Dependent Claim
29 words
A method according to claim 4 wherein the memory cells are floating gate type electrically programmable read-only memory cells, and the gate electrodes are control gates for the cells.
Claim 11
Dependent Claim
17 words
A method according to claim 9 wherein floating gates are formed beneath each of said gate electrodes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-07 | 1986-08-09 | 1987-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-07 | 1990-08-09 | 1991-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-07 | 1994-08-09 | 1995-02-08 | $7700.00 | Window Closed / Lapsed |