US4980309A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making high density EEPROM
Assignee: Texas Instruments Inc
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Filing: 1989-06-14
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Granted: 1990-12-25
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Expires: 2009-06-14
Abstract
Abstract An electrically erasable, programmable read only memory (EEPROM) having an erase window directly overlying both a control gate layer (24) and a column line (12) is disclosed. Column lines (12) are implanted into a semiconductor substrate (16) and covered with a first insulating layer (18). A floating gate layer (20) overlies the first insulating layer (18) and is covered with a second insulating layer (22). The control gate layer (24) overlies the control insulating layer (22) and is covered by a third insulating layer (26). A passage (28) extends through the third insulating layer (26), control gate layer (24) and second insulating layer (22) and contains a sidewall insulator (30) on walls thereof. A tunnel oxide (32) resides within the passage (28) and is contacted by a programming electrode layer (34) which additionally overlies the third insulating layer (26) and fills the passage (28).
Inventors
- 👤 Allan T. Mitchell
- 👤 Bert R. Riemenschneider
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:52
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
187 words
A method of manufacturing an electrically erasable, programmable memory cell formed at semiconductor surface area of a first conductivity type, said method comprising the steps of: forming a column line of a second conductivity type at the surface area, said forming a column line step additionally defining an active region adjacent the column line; forming a first insulating layer overlying the column line and active region; forming a first conducting layer overlying the first insulating layer and having a portion thereof extending over the active region; forming a second insulating layer overlying said first conducting layer; forming a second conducting layer overlying the second insulating layer; forming a third insulating layer overlying the second conducting layer; forming a passage through the third insulating layer, second conducting layer, and second insulating layer, said passage formed adjacent said column line and remote from said active region; forming a fourth insulating layer on the first conducting layer within said passage of said forming a passage step; and forming a programming electrode within said passage and overlying said fourth insulating layer such that said electrode is remote from said active region.
Claim 2
Independent Claim
187 words
A method of manufacturing an electrically erasable, programmable memory cell formed at semiconductor surface area of a first conductivity type, said method comprising the steps of: forming a column line of a second conductivity type at the surface area, said forming a column line step additionally defining an active region adjacent the column line; forming a first insulating layer overlying the column line and active region; forming a first conducting layer overlying the first insulating layer and having a portion thereof extending over the active region; forming a second insulating layer overlying said first conducting layer; forming a second conducting layer overlying the second insulating layer; forming a third insulating layer overlying the second conducting layer; forming a passage through the third insulating layer, second conducting layer, and second insulating layer, said passage formed adjacent said column line and remote from said active region; forming a fourth insulating layer on the first conducting layer within said passage of said forming a passage step; and forming a programming electrode within said passage and overlying said fourth insulating layer such that said electrode is remote from said active region.
Claim 3
Dependent Claim
34 words
A method as claimed in claim 1 additionally comprising the step of forming, prior to said forming a fourth insulating layer step, a sidewall insulator within said passage of said forming a passage step.
Claim 4
Dependent Claim
22 words
A method as claimed in claim 1 wherein said forming a first conducting layer step comprises the step of depositing polycrystalline silicon.
Claim 5
Dependent Claim
23 words
A method as claimed in claim 3 wherein said depositing step comprises the step of maintaining said polycrystalline silicon in an amorphous state.
Claim 6
Dependent Claim
33 words
A method as claimed in claim 4 additionally comprising the step of implanting a dopant in said polycrystalline silicon during said maintaining step and prior to said forming a second insulating layer step.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-24 | 1994-06-25 | 1994-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-24 | 1998-06-25 | 1998-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-24 | 2002-06-25 | 2002-12-25 | $7700.00 | Window Closed / Lapsed |