Process for the production of a memory cell

Claim 1

Process for the production of an integrated memory cell on a semiconductor substrate having a matrix of memory points electrically insulated from one another, each memory point comprising a drain, a source, a gate and a gate control line, said process comprising the following steps: (a) a first step of defining the gates of the memory points and their control line involving the following operations: (a1) producing a stack of materials, whereof at least one is conductive and is in the form of first parallel strips aligned in a first direction (Y), for producing a gate of memory points and whereof at least one other is constituted by a conductive layer for producing the control lines of the gates, (a2) producing a group of second parallel strips, aligned in a second direction (X) perpendicular to the first direction (Y), said strips having at least one insulating material layer, (a3) producing spacers on each flank of said second strips, said spacers forming strips in the second direction (X), said gates being defined by superimposing zones of said spacers and said first strips, the control lines being defined by the spacers, (b) a second step of producing sources of memory points involving the following operations: (b1) etching layers not protected by spacers or by materials consituting the second strips, (b2) doping the substrate exposed by said etching operation, (b3) deposition of an insulating material on the doped zones, (c) a third step of producing drains of memory points involving the following operations: (c1) elimination by etching of the materials constituting the second strips, (c2) elimination by complete or partial etching of the materials constituting the stack exposed during the previous etching operation, (c3) doping the substrate in the regions etched in the preceding step, (c4) insulating of the drain-side flanks of the gates exposed by the preceding etching operations, (d) a fourth stage of producing parallel conductive lines, aligned in accordance with the first direction, said conductive lines being electrically connected to the drains of the memory points.