Process for fabricating an eprom cell array organized in a tablecloth arrangement

Claim 1

A process for fabricating an integrated EPROM cell memory matrix having source and drain lines parallel among each other between parallel strips of isolation field oxide, floating gate areas between said source and drain lines, control gate lines parallel among each other and running perpendicularly to said source and drain lines and over said floating gate areas, which comprises oxidizing the surface of a monocrystalline silicon wafer, depositing a nitride layer, masking the active cell areas, patterning by etching through the mask said nitride layer and implanting field isolation areas, removing the residual masking resist, growing an isolation field oxide, etching the patterned nitride layer and the underlying oxidized silicon layer, masking the area destined to the formation of said integrated matrix, implanting active areas of the EPROM cells, removing the masking resist, forming a layer of gate oxide over the active areas and depositing a first layer of polycrystalline silicon, doping said polycrystalline silicon, and characterized by comprising the following steps a) forming an electrically insulating dielectric layer over the surface of said first layer of deposited polycrystalline silicon; b) depositing a second layer of polycrystalline silicon; c) forming a photoresist mask defining in a longitudinal sense a gate structure of said EPROM cells; d) etching through said photoresist mask the stack of layers formed by said second polycrystalline silicon layer, said dielectric insulating layer, said first polycrystalline silicon first layer and said gate oxide layer; e) implanting and reoxidizing the source and drain areas adjacent to said longitudinally defined gate structure of the EPROM cells, and f) conformally depositing an isolation dielectric layer, depositing a planarization layer of dielectric material, etching said planarization layer and said conformally deposited isolation layer until exposing the surface of said second layer of polycrystalline silicon, masking the area occupied by said matrix of EPROM cells, etching the second layer of polycrystalline silicon and said electrically insulating layer, removing the residual masking resist, and further characterized by comprising the following steps: i) depositing a third layer of polycrystalline silicon; ii) doping said third layer of polycrystalline silicon and through the latter also the contiguous underlying second layer of polycrystalline silicon; iii) depositing a silicide layer; iv) forming a photoresist mask for defining, in a transversal sense, said gate structure of the EPROM cells and said control gate lines; v) etching through the latter photoresist mask a second stack formed by said silicide layer, said third layer of polycrystalline silicon for patterning said control gate lines and said second layer of polycrystalline silicon, and continuing the etching, in a substantially self-alignment condition, of the said electrically insulating layer and of said first layer of polycrystalline silicon for patterning said gate structures in a transversal sense; vi) performing a further isolation enrichment implantation of the source and drain areas of the monocrystalline silicon exposed by the preceding etching of the said second stack of layers.