Method of making contract-free floating-gate memory array with silicided buried bitlines and with single-step defined floating gates

Claim 1

A method for making a non-volatile memory cell array including bitlines and wordlines in a face of a semiconductor substrate of first conductivity type, comprising the steps of: forming field oxide regions with underlying channel stop regions in said face, said field oxide regions separated by at least channels; growing a gate oxide layer over said channels and said field oxide regions; applying a first conductive layer on said face over said gate oxide layer; applying a second conductive layer on said face overlying and insulated from said first conductive layer by an inter-level dielectric layer; forming a protective layer over said second conductive layer; patterning said protective layer and forming control-gates from said second conductive layer and forming floating-gates from said first conductive layer such that said floating:gates are substantially centered over said channels between said field oxide regions and such that said gates extend over a part of said field oxide regions, said floating-gates having sides; forming a single-step, thermally grown oxide layer on at least said sides of said floating-gates; using at least said control-gates as a mask, implanting an impurity material of second conductivity type; forming said bitlines in the implanted regions of said face; siliciding said bitlines; forming an insulating oxide region in the space between said control- and floating-gates and over said bitlines and said field oxide regions; removing a part of said insulating oxide region and substantially all of said protective layer to form a surface substantially planar including the upper surface of said control gates; applying a third conductive layer to said substantially planar surface; and patterning said third conductive layer and etching through said third conductive layer to form said wordlines over said control gates and in contact with said control gates.

Claim 2

A method for making a non-volatile memory cell array including bitlines and wordlines in a face of a semiconductor substrate of first conductivity type, comprising the steps of: forming field oxide regions with underlying channel stop regions in said face, said field oxide regions separated by at least channels; growing a gate oxide layer over said channels and said field oxide regions; applying a first conductive layer on said face over said gate oxide layer; applying a second conductive layer on said face overlying and insulated from said first conductive layer by an inter-level dielectric layer; forming a protective layer over said second conductive layer; patterning said protective layer and forming control-gates from said second conductive layer and forming floating-gates from said first conductive layer such that said floating:gates are substantially centered over said channels between said field oxide regions and such that said gates extend over a part of said field oxide regions, said floating-gates having sides; forming a single-step, thermally grown oxide layer on at least said sides of said floating-gates; using at least said control-gates as a mask, implanting an impurity material of second conductivity type; forming said bitlines in the implanted regions of said face; siliciding said bitlines; forming an insulating oxide region in the space between said control- and floating-gates and over said bitlines and said field oxide regions; removing a part of said insulating oxide region and substantially all of said protective layer to form a surface substantially planar including the upper surface of said control gates; applying a third conductive layer to said substantially planar surface; and patterning said third conductive layer and etching through said third conductive layer to form said wordlines over said control gates and in contact with said control gates.