Production of an integrated memory cell

Claim 2

Method to produce an EPROM or EEPROM type integrated memory cell on a semi-conductive substrate comprising a matrix of memory points electrically insulated from each other, each memory point comprising a source, a drain, a floating gate, a control grid and a channel situated under the floating gate, the source and the drain being situated on both sides of the floating gate, the floating gate of each memory point being laterally distant and insulated along a first direction from one or two other floating gates, said method comprising a stage for forming lateral insulations of the floating gates along the first direction by insulating relief patterns followed by a stage for forming the actual floating gates by depositing and etching.

Claim 3

Production method according to claim 1, wherein in order to form the lateral insulations between the floating gates, an etching mask is used comprising defining the length of the floating gates, the etching mask used comprising one grid pattern out of two, the pattern of the mask having a pitch, which corresponds to two lengths of floating gates, increased by two lengths of spaces separating two grids.

Claim 4

Production method according to claim 1, wherein the formation of the floating gates comprises a stage for depositing a sacrificial layer and then an etching of this layer by means of a mask having one grid pattern out of two, followed by a depositing of an insulating layer and then an etching of the nonconductor so as to form the spacer type insulating relief pattern of the desired submicronic width, and finally eliminating the sacrificial layer.

Claim 5

Method according to claim 1, said method comprising the following stages: (a) firstly: formation in the substrate of active zones separated by the thick oxide forming the field oxide insulating the memory points, formation of a layer of material serving to protect the substrate, doping of the channel regions by ionic implantation through the protection layer, (b) then formation of the lateral insulations by: the depositing of the sacrificial layer, the etching of this layer so as to obtain the desired patterns, the depositing of the thin insulating layer, the etching of the nonconductor so as to embody the spacer type insulating relief patterns against the lateral edges of the patterns of the etched sacrificial layer, the elimination of the patterns of the sacrificial layer, the elimination of the protection layer, the formation of a thin layer of an insulating material so as to form a grid oxide, (c) formation of the floating gates by depositing and etching, (d) formation of the control grids by depositing, masking and etching, (e) formation of the sources and drains, (f) formation of the contacts, (g) formation of the interconnections.

Claim 6

Method according to claim 4, wherein the formation of the floating gates comprises the following stages: depositing of a planarization resin layer, engraving at identical speed the resin and polycrystalline silicon allowing the polycrystalline silicon to be exposed, doping of the first layer of polycrystalline silicon.

Claim 7

Method according to claim 4, wherein the sacrificial layer is constituted by polycrystalline silicon.

Claim 8

Method according to claim 4, wherein the substrate is silicon and in which the thin layer of insulating material is a silicon oxide formed by oxidation of the substrate.

Claim 9

Method according to claim 4, wherein the protection layer is constituted by the nitride mask used to form the field oxide.

Claim 10

Method according to claim 5, wherein the doping of the first layer of polycrystalline silicon is carried out immediately after this layer is deposited.

Claim 11

Method according to claim 3, wherein the formation of the control grids comprises the following successive stages: depositing of the insulating inter-grid layer; depositing of a second layer of polycrystalline silicon; doping of the second layer of polycrystalline silicon; etching of this second layer from a mask having patterns defining the control grids; partial etching of the insulating layer forming the spacers and the inter-grid insulating layer in those zones where these layers are not overlapped by the second layer of polycrystalline silicon; selective etching of the first layer of polycrystalline silicon with respect to the nonconductor in those zones not overlapped by the second polycrystalline silicon layer.