US4373250A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating a high capacity memory cell
Assignee: Signetics Corp
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Filing: 1980-11-17
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Granted: 1983-02-15
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Expires: 2000-11-17
Abstract
Abstract A method of fabricating an array of high capacity memory cells comprises forming a transfer gate over each cell area spaced from an adjacent isolation region to define a storage region in the semiconductor surface between the transfer gate and isolation region and to define a bit line region on the other side of the transfer gate; forming a shallow ion layer of first conductivity type in the storage region self-aligned with the transfer gate; forming a deep ion layer of opposite conductivity type in the storage region self-aligned with the transfer gate; forming a storage gate over a portion of the storage region spaced laterally from the transfer gate to form a gap between the storage and transfer gates; and introducing ions of the first conductivity type into the portion of the storage region defined by the gap to at least neutralize some ions in the deep ion layer.
Inventors
- 👤 Manohar L. Malwah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:07
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
256 words
A method of fabricating an array of high capacity memory cells, comprising: (a) forming isolation regions in a surface of a semiconductor substrate which are patterned to form a multiplicity of cell areas; (b) forming a pattern of conductive material over said semiconductor surface insulated therefrom to form a transfer gate over each cell area spaced from an adjacent isolation region and to define a storage region in said semiconductor surface adjacent to one side of said transfer gate between said transfer gate and said adjacent isolation region and also to define a bit line region on the other side of said transfer gate; (c) introducing ions having majority carriers of first conductivity type in said storage region to form a shallow ion layer therein self-aligned with said transfer gate; (d) introducing ions having majority carriers of second conductivity type opposite said first conductivity type in said storage region to form a deep ion layer beneath said shallow ion layer self-aligned with said transfer gate; (e) forming a storage gate of conductive material over a portion of said storage region and spaced laterally from said transfer gate to form a gap between said storage and transfer gates; and (f) introducing ions having majority carriers of said first conductivity type into the portion of said storage region defined by said gap and into said bit line region to at least neutralize some of the ions in said deep ion layer and also to produce a bit line which may serve as the source region of a transistor.
Claim 2
Independent Claim
256 words
A method of fabricating an array of high capacity memory cells, comprising: (a) forming isolation regions in a surface of a semiconductor substrate which are patterned to form a multiplicity of cell areas; (b) forming a pattern of conductive material over said semiconductor surface insulated therefrom to form a transfer gate over each cell area spaced from an adjacent isolation region and to define a storage region in said semiconductor surface adjacent to one side of said transfer gate between said transfer gate and said adjacent isolation region and also to define a bit line region on the other side of said transfer gate; (c) introducing ions having majority carriers of first conductivity type in said storage region to form a shallow ion layer therein self-aligned with said transfer gate; (d) introducing ions having majority carriers of second conductivity type opposite said first conductivity type in said storage region to form a deep ion layer beneath said shallow ion layer self-aligned with said transfer gate; (e) forming a storage gate of conductive material over a portion of said storage region and spaced laterally from said transfer gate to form a gap between said storage and transfer gates; and (f) introducing ions having majority carriers of said first conductivity type into the portion of said storage region defined by said gap and into said bit line region to at least neutralize some of the ions in said deep ion layer and also to produce a bit line which may serve as the source region of a transistor.
Claim 3
Dependent Claim
14 words
The invention according to claim 1, wherein said substrate comprises second conductivity type material.
Claim 4
Dependent Claim
14 words
The invention according to claim 2, wherein said substrate comprises P type conductivity material.
Claim 5
Dependent Claim
43 words
The invention according to claim 1, wherein said pattern of conductive material forms two transfer gates in each cell area that are spaced apart by a single bit line region, with each transfer gate spaced from an isolation region by a storage region.
Claim 6
Dependent Claim
47 words
The invention according to claim 1, wherein said pattern of conductive material extends over a peripheral region adjacent to a cell area and forms a peripheral transfer gate spaced from an isolation region to define regions on opposite sides thereof for the formation of source and drain.
Claim 7
Dependent Claim
57 words
The invention according to claim 1 and further including forming a layer of insulating material over said storage gate, and forming an additional pattern of conductive material over said transfer gate and said layer of insulating material in contact with said transfer gate and overlapping but insulated from said storage gate by said layer of insulating material.
Claim 8
Dependent Claim
22 words
The invention according to claim 6, wherein the conductive material in steps (b) and (e) and said additional pattern comprise doped polysilicon.
Claim 9
Dependent Claim
35 words
The invention according to claim 1, wherein said semiconductor substrate is formed of silicon and step (b) is preceded by forming on the substrate an oxide insulating layer upon which said conductive pattern is produced.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-14 | 1986-08-16 | 1987-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-14 | 1990-08-16 | 1991-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-14 | 1994-08-16 | 1995-02-15 | $7700.00 | Window Closed / Lapsed |