Patent EP0000667A1 successfully refreshed from Google Patents.
US4115871A
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US
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MOS random memory array
Assignee: National Semiconductor Corp
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Filing: 1977-04-19
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Granted: 1978-09-19
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Expires: 1997-04-19
Abstract
Abstract This disclosure relates to an MOS random access memory array which utilizes a very small memory cell having a single MOS device and a small size, high capacitance, semiconductor capacitor device connected together to form one bit or memory cell of an MOS dynamic, random access memory array. Preferably, either the source or drain region of the MOS device is connected to the semiconductor portion of the semiconductor capacitor device which is of the electrode-insulator-semiconductor type. The semiconductor capacitor has a very high capacitance due to the use of a very shallow arsenic (N type) implanted region within a boron (P type) implanted region so that the PN junction formed is located where the concentration of Boron impurities is high thereby increasing the capacitance of the semiconductor capacitor. For each memory cell of the memory array, one of the active regions of the MOS device, for example, the source region, is connected to a Bit/Sense line of the memory array. The semiconductor portion of the semiconductor capacitor is connected to the drain region of the MOS device and the electrode plate of the semiconductor capacitor device that is not connected to the drain region of the MOS device is connected to a word line which word line is the next adjacent word line of the MOS random access memory array. The gate of the MOS device is connected up to the word line for that MOS device.
Inventors
- 👤 Andrew G. Varadi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 03:34
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/4074; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
396 words
An MOS random access memory array comprising, in combination, a plurality of interconnected memory cells, means for writing information into said memory cells, means for reading information contained in said memory cells, each of said memory cells comprising an MOS device having source and drain regions and a gate electrode and a semiconductor capacitor device connected to said MOS device, said semiconductor capacitor device of each of said memory cells comprising a first semiconductor region of one conductivity type having a high resistivity, a second semiconductor region of said one conductivity type located within a portion of said first semiconductor region extending inwardly from one surface thereof and having a lower resistivity than the resistivity of said first semiconductor region, a region of opposite conductivity type located within said second semiconductor region and having a lower resistivity than the resistivity of said second semiconductor region, an insulating layer located on said one surface and in contact with said first and second regions of said one conductivity type and said region of opposite conductivity type, an electrically conductive electrode disposed on a portion of said insulating layer located over said region of opposite conductivity type, and contact means connected to one of the source and drain regions of said MOS device, said electrically conductive electrode being one plate of the semiconductor capacitor device, said electrically conductive electrode being connected to the gate electrode of another MOS device of one of said plurality of memory cells, said insulating layer being the dielectric of the semiconductor capacitor device, and said region of opposite conductivity type being the other plate of the semiconductor capacitor device, said region of opposite conductivity type of the semiconductor capacitor device being in contact with the other of said source and drain regions of said MOS device, said gate electrode of said MOS device being in electrical contact with an electrically conductive electrode plate of another semiconductor capacitor device coupled to said another MOS device, a plurality of word lines and a plurality of bit/sense lines, each of said memory cells being connected to two adjacent word lines and one bit/sense line, each one of said memory cells having an adjacent memory cell, said each one of said memory cells being connected to one of said plurality of bit/sense lines and said adjacent memory cell being connected to another of said plurality of bit/sense lines.
Claim 2
Dependent Claim
396 words
An MOS random access memory array comprising, in combination, a plurality of interconnected memory cells, means for writing information into said memory cells, means for reading information contained in said memory cells, each of said memory cells comprising an MOS device having source and drain regions and a gate electrode and a semiconductor capacitor device connected to said MOS device, said semiconductor capacitor device of each of said memory cells comprising a first semiconductor region of one conductivity type having a high resistivity, a second semiconductor region of said one conductivity type located within a portion of said first semiconductor region extending inwardly from one surface thereof and having a lower resistivity than the resistivity of said first semiconductor region, a region of opposite conductivity type located within said second semiconductor region and having a lower resistivity than the resistivity of said second semiconductor region, an insulating layer located on said one surface and in contact with said first and second regions of said one conductivity type and said region of opposite conductivity type, an electrically conductive electrode disposed on a portion of said insulating layer located over said region of opposite conductivity type, and contact means connected to one of the source and drain regions of said MOS device, said electrically conductive electrode being one plate of the semiconductor capacitor device, said electrically conductive electrode being connected to the gate electrode of another MOS device of one of said plurality of memory cells, said insulating layer being the dielectric of the semiconductor capacitor device, and said region of opposite conductivity type being the other plate of the semiconductor capacitor device, said region of opposite conductivity type of the semiconductor capacitor device being in contact with the other of said source and drain regions of said MOS device, said gate electrode of said MOS device being in electrical contact with an electrically conductive electrode plate of another semiconductor capacitor device coupled to said another MOS device, a plurality of word lines and a plurality of bit/sense lines, each of said memory cells being connected to two adjacent word lines and one bit/sense line, each one of said memory cells having an adjacent memory cell, said each one of said memory cells being connected to one of said plurality of bit/sense lines and said adjacent memory cell being connected to another of said plurality of bit/sense lines.
Claim 3
Dependent Claim
74 words
An MOS random access memory array in accordance with claim 1 wherein said gate electrode of said MOS device being connected to one of said two adjacent word lines, said electrically conductive plate electrode of said capacitor device being electrically connected to the other of said two adjacent word lines, said contact means connected to one of the source and drain regions of said MOS device being also connected to said one bit/sense line.
Claim 4
Dependent Claim
57 words
An MOS random access memory array in accordance with claim 2 including word driver means connected to each of said plurality of word lines for applying a signal on a selected word line, and sense amplifier means connected to each of said plurality of bit/sense lines for sensing the magnitude of a signal on said bit/sense line.
Claim 5
Dependent Claim
63 words
An MOS random access memory array in accordance with claim 1, wherein said first semiconductor region of one conductivity type being a P- substrate region, said second semiconductor region of said one type conductivity being a P region, said region of opposite conductivity type being an N region, and the source and drain regions of said MOS device being of N+ type conductivity.
Claim 6
Dependent Claim
49 words
An MOS random access memory array in accordance with claim 4 wherein said second semiconductor region being a boron implanted P region, said region of opposite conductivity type being an arsenic implanted N region, and said source and drain regions of said MOS device being phosphorous diffused N+ regions.
Claim 7
Dependent Claim
71 words
An MOS random access memory array in accordance with claim 4 wherein the junction depth of said boron implanted second semiconductor region with said first semiconductor region being several times greater than the junction depth of said arsenic implanted region with said boron implanted second semiconductor region, the junction depth of said source and drain regions of said MOS device being greater than the junction depth of said arsenic implanted region.
Claim 8
Dependent Claim
33 words
An MOS random access memory array in accordance with claim 1 wherein said gate elecrode of said MOS device and said electrically conductive electrode of said semiconductor capacitor device being doped polysilicon elecrodes.
Claim 9
Dependent Claim
56 words
An MOS random access memory array in accordance with claim 1 wherein said electrically conductive electrode of said semiconductor device being located over said region of opposite conductivity type and confined within the area formed by the PN junction located between said second region of said one conductivity type and said region of opposite conductivity type.
Claim 10
Dependent Claim
332 words
An MOS random access memory array in accordance with claim 1 wherein said gate electrode of said MOS device being connected to one of said two adjacent word lines, said electrically conductive plate electrode of said capacitor device being electrically connected to the other of said two adjacent word lines, said contact means connected to one of the source and drain regions of said MOS device being also connected to said one bit/sense line, including word driver means connected to each of said plurality of word lines for applying a signal on a selected word line, and sense amplifier means connected to each of said plurality of bit/sense lines for sensing the magnitude of a signal on said bit/sense line, said gate electrode of said MOS device and said electrically conductive electrode of said semiconductor capacitor device being doped polysilicon electrodes, said electrically conductive electrode of said semiconductor capacitor being located over said region of opposite conductivity type and confined within the area formed by the PN junction located between said second region of said one conductivity type and said region of opposite conductivity type, said first semiconductor region of one conductivity type being a P- substrate region, said second semiconductor region of said one type conductivity being a P region, said region of opposite conductivity type being an N region, and the source and drain regions of said MOS device being of N+ type conductivity, said second semiconductor region being a boron implanted P region, said region of opposite conductivity type being an arsenic implanted N region, and said source and drain regions of said MOS device being phosphorous diffused N+ regions, the junction depth of said boron implanted second semiconductor region with said first semiconductor region being several times greater than the junction depth of said arsenic implanted region with said boron implanted second semiconductor region, the junction depth of said source and drain regions of said MOS device being greater than the junction depth of said arsenic implanted region.
Claim 11
Dependent Claim
203 words
An MOS random access memory array comprising, in combination, a plurality of interconnected memory cells, means for writing information into said memory cells, means for reading information contained in said memory cells, each of said memory cells comprising an MOS device having source and drain regions and a gate electrode and a semiconductor capacitor device connected to said MOS device, said semiconductor capacitor device of each of said memory cells having an electrically conductive electrode as one plate of the semiconductor capacitor device, said electrically conductive electrode being connected to the gate electrode of another MOS device of one of said plurality of memory cells, said gate electrode of said MOS device being in electrical contact with an electrically conductive electrode plate of another semiconductor capacitor device coupled to said another MOS device, a plurality of word lines and a plurality of bit/sense lines, each of said memory cells being connected to two adjacent word lines and one bit/sense line, each one of said memory cells having an adjacent memory cell, said each one of said memory cells being connected to one of said plurality of bit/sense lines and said adjacent memory cell being connected to another of said plurality of bit/sense lines.
Claim 12
Dependent Claim
203 words
An MOS random access memory array comprising, in combination, a plurality of interconnected memory cells, means for writing information into said memory cells, means for reading information contained in said memory cells, each of said memory cells comprising an MOS device having source and drain regions and a gate electrode and a semiconductor capacitor device connected to said MOS device, said semiconductor capacitor device of each of said memory cells having an electrically conductive electrode as one plate of the semiconductor capacitor device, said electrically conductive electrode being connected to the gate electrode of another MOS device of one of said plurality of memory cells, said gate electrode of said MOS device being in electrical contact with an electrically conductive electrode plate of another semiconductor capacitor device coupled to said another MOS device, a plurality of word lines and a plurality of bit/sense lines, each of said memory cells being connected to two adjacent word lines and one bit/sense line, each one of said memory cells having an adjacent memory cell, said each one of said memory cells being connected to one of said plurality of bit/sense lines and said adjacent memory cell being connected to another of said plurality of bit/sense lines.
References Cited (Backward Citations)
US3699537A
Cited
US3838404A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-09-18 | 1982-03-20 | 1982-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-09-18 | 1986-03-20 | 1986-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-09-18 | 1990-03-20 | 1990-09-19 | $7700.00 | Window Closed / Lapsed |