Random access memory system and cell

Claim 2

An amplifier for sensing and refreshing charges stored in a plurality of memory capacitances comprising: a pair of field-effect transistors, each having a control electrode and first and second terminals, cross-coupled so that the control electrode of each field-effect transistor is coupled to the first terminal of the other field-effect transistor, the second terminals of the field-effect transistors being coupled together; first and second resistance coupled respectively to the first terminals of the pair of field-effect transistors; first and second load capacitances of equal value coupled respectively to the first terminals of the pair of field-effect transistors; means for coupling a selected one of the plurality of memory capacitances to a selected one of the first and second load capacitance so that the selected memory capacitance is added to the selected load capacitance thereby making the first and second load capacitances unequal; and means, coupled to the first and second resistance means, for charging the first and second load capacitances toward a predetermined charging potential so that the selected load capacitance will reach the predetermined potential first if the selected memory capacitance was initially charged and so that the remaining load capacitance will reach the predetermined potential first if the selected memory capacitance was not initially charged, the pair of cross-coupled field-effect transistors being switched by the load capacitance which first reaches the predetermined potential so that the remaining load capacitance is discharged to zero potential.

Claim 3

An amplifier in accordance with claim 1 wherein said first and second resistance means comprise first and second feld-effect transistors, each having a control electrode and first and second terminals, the second terminal of the first and second field-effect transistors being respectively coupled to the first terminals of said pair of field-effect transistors and the first terminals of the first and second field-effect transistors being coupled to said means for charging.

Claim 4

means for discharging the second load capacitance to ground whenever the first load capacitance charges faster, while permitting full charging of the first load capacitance and the memory capacitor, in parallel, from the source by the time t2.

Claim 5

means for discharging the second load capacitance to ground whenever the first load capacitance charges faster, while permitting full charging of the first load capacitance and the memory capacitor, in parallel, from the source by the time t2.

Claim 6

to read out from any selected memory cell in the first bank, the inverted signal stored on the memory cell in the first bank is applied to node 1, re-inverted by the inverting means at node 2, and then read out from node 2 in its normal form; I. the data being written in normal form on the memory cells in the second bank, and being rEad out from node 2 in normal form.

Claim 7

to read out from any selected memory cell in the first bank, the inverted signal stored on the memory cell in the first bank is applied to node 1, re-inverted by the inverting means at node 2, and then read out from node 2 in its normal form; I. the data being written in normal form on the memory cells in the second bank, and being rEad out from node 2 in normal form.

Claim 8

allowing completion of the charge from the source to the memory capacitor whenever the first load capacitance charges faster, which charge is the desired predetermined charge VM, thus refreshing the charge originally stored; and F. means for isolating the memory capacitor from the refresh circuit after the memory has been (1) fully discharged to ground or (2) fully charged from the source, and before subsequent operation of the means (B).

Claim 9

allowing completion of the charge from the source to the memory capacitor whenever the first load capacitance charges faster, which charge is the desired predetermined charge VM, thus refreshing the charge originally stored; and F. means for isolating the memory capacitor from the refresh circuit after the memory has been (1) fully discharged to ground or (2) fully charged from the source, and before subsequent operation of the means (B).

Claim 10

if the memory capacitor was previously charged to a voltage at or near VM, the charge on the memory capacitor adds to the source potential to charge the first load capacitance at a faster rate; D. discharging the memory capacitor to ground whenever the second load capacitance charges faster, thus refreshing the ground potential originally stored on the memory capacitor; E. allowing completion of the charge from the source to the memory capacitor whenever the first load capacitance charges faster, which charge is the desired predetermined charge VM, thus refreshing the charge originally stored; and F. isolating the memory capacitor after it has been (1) fully discharged to ground or (2) fully charged from the source, and before a subsequent performance of step A.

Claim 11

if the memory capacitor was previously charged to a voltage at or near VM, the charge on the memory capacitor adds to the source potential to charge the first load capacitance at a faster rate; D. discharging the memory capacitor to ground whenever the second load capacitance charges faster, thus refreshing the ground potential originally stored on the memory capacitor; E. allowing completion of the charge from the source to the memory capacitor whenever the first load capacitance charges faster, which charge is the desired predetermined charge VM, thus refreshing the charge originally stored; and F. isolating the memory capacitor after it has been (1) fully discharged to ground or (2) fully charged from the source, and before a subsequent performance of step A.

Claim 12

if the memory capacitor was previously charged to a voltage at or near VM, the charge on the memory capacitor adds to the source potential to charge the first load capacitance at a faster rate; E. means responsive to a differential charging rate between the first and second load capacitances for

Claim 13

if the memory capacitor was previously charged to a voltage at or near VM, the charge on the memory capacitor adds to the source potential to charge the first load capacitance at a faster rate; E. means responsive to a differential charging rate between the first and second load capacitances for

Claim 14

allowing completion of the charge from the source to the cell capacitor whenever the first load capacitance charges faster, which charge is the desired predetermined charge VM, thus refreshing the charge originally stored; the selective connecting means (claim 11) operating to isolate the cell capacitor from the refresh circuit after the cell capacitor has been (1) fully discharged to ground or (2) fully charged from the source, and before a subsequent operation of the means (B).

Claim 15

if the cell capacitor was previously charged to a voltage at or near VM, the charge on the cell capacitor adds to the source potential to charge the first load capacitance at a faster rate; and D. means responsive to a differential charging rate between the first and second load capacitances for

Claim 16

if the cell capacitor was previously charged to a voltage at or near VM, the charge on the cell capacitor adds to the source potential to charge the first load capacitance at a faster rate; and D. means responsive to a differential charging rate between the first and second load capacitances for

Claim 17

to read out a signal from any selected memory cell in the first bank, the inverted signal stored on the memory cell in the first bank is applied to the first node, re-inverted, and transmitted from the second node to the read out circuit in its normal form; the data being written and read from the memory cells of the second bank in normal form.

Claim 18

to read out a signal from any selected memory cell in the first bank, the inverted signal stored on the memory cell in the first bank is applied to the first node, re-inverted, and transmitted from the second node to the read out circuit in its normal form; the data being written and read from the memory cells of the second bank in normal form.

Claim 19

An amplifier in accordance with claim 2 wherein said means for charging further comprises a source of single-phase clock signals.

Claim 20

An amplifier for sensing and refreshing charges stored in a plurality of memory capacitances comprising: a pair of field-effect transistors, each having a control electrode and first and second terminals, cross-coupled so that the control electrode of each field-effect transistor is coupled to the first terminal of the other field-effect transistor, the second terminals of the field-effect transistors being coupled together; first and second load capacitances of equal value coupled respectively to the first terminals of the pair of field-effect transistors; means for coupling a selected one of the plurality of memory capacitances to a selected one of the first and second load capacitances so that the selected memory capacitance is added to the selected load capacitance thereby making the first and second load capacitances unequal; and means, coupled to the pair of field-effect transistors, for charging the first and second load capacitances toward a predetermined charging potential so that the selected load capacitance will reach the predetermined potential first if the selected memory capacitance was initially charged and so that the remaining load capacitance will reach the predetermined potential first if the selected memory capacitance was not initally charged, the pair of cross-coupled field-effect transistors being switched by The load capacitance which first reaches the predetermined potential so that the remaining load capacitance is discharged to zero potential.

Claim 21

An amplifier for sensing and refreshing charges stored in a plurality of memory capacitances comprising: a pair of field-effect transistors, each having a control electrode and first and second terminals, cross-coupled so that the control electrode of each field-effect transistor is coupled to the first terminal of the other field-effect transistor, the second terminals of the field-effect transistors being coupled together; first and second load capacitances of equal value coupled respectively to the first terminals of the pair of field-effect transistors; means for coupling a selected one of the plurality of memory capacitances to a selected one of the first and second load capacitances so that the selected memory capacitance is added to the selected load capacitance thereby making the first and second load capacitances unequal; and means, coupled to the pair of field-effect transistors, for charging the first and second load capacitances toward a predetermined charging potential so that the selected load capacitance will reach the predetermined potential first if the selected memory capacitance was initially charged and so that the remaining load capacitance will reach the predetermined potential first if the selected memory capacitance was not initally charged, the pair of cross-coupled field-effect transistors being switched by The load capacitance which first reaches the predetermined potential so that the remaining load capacitance is discharged to zero potential.

Claim 22

An amplifier in accordance with claim 4 wherein said means for charging further comprises: a third field-effect transistor, having a control electrode and first and second terminals, the first and second terminals of the third field-effect transistor being coupled in parallel with the first and second terminals of one of the pair of field-effect transistors; a fourth field-effect transistor, having a control electrode and first and second terminals, the first and second terminals of the fourth field-effect transistor being coupled in parallel with the first and second terminals of the remaining one of the pair of field-effect transistors; and a source of single-phase clock signals coupled to the control electrodes of the third and fourth field-effect transistors.

Claim 23

An amplifier in accordance with claim 5 wherein each of said field-effect transistors is of the MOSFET type with the control electrode and the first and second terminals thereof comprising gate, drain, and source electrodes.

Claim 24

A memory cell of the capacitive storage type comprising: a field-effect transistor, having a control electrode and first and second terminals; a plurality of address conductors, one of the plurality of address conductors being coupled to the control electrode of the field-effect transistor; an input-output conductor coupled to the first terminal of the field-effect transistor; and a capacitance for storing charges having first and second electrodes, the first electrode being coupled to the second terminal of the field-effect transistor and the second electrode being coupled to a remaining one of the plurality of address conductors.

Claim 25

A memory cell of the capacitive storage type comprising: a field-effect transistor, having a control electrode and first and second terminals; a plurality of address conductors, one of the plurality of address conductors being coupled to the control electrode of the field-effect transistor; an input-output conductor coupled to the first terminal of the field-effect transistor; and a capacitance for storing charges having first and second electrodes, the first electrode being coupled to the second terminal of the field-effect transistor and the second electrode being coupled to a remaining one of the plurality of address conductors.

Claim 26

A memory cell in accordance with claim 7 wherein the field-effect transistor is of the MOSFET type and the first electrode of the capacitance is formed integrally with the second terminal of the field-effect transistor.

Claim 27

A memory cell in accordance with claim 7 wherein the second electrode of the capacitance is formed integrally with said remaining one of the plurality of address conductors.

Claim 28

A memory cell in accordance with claim 7 wherein the plurality of address conductors are parallel to each other and wherein the second terminal of the capacitance is coupled to one of the plurality of address conductors which is adjacent to the address conductor to which the control electrode of the field-effect transistor is coupled.

Claim 29

A memory cell of the capacitive storage type, comprising: a capacitor; an input/output conductor for the capacitor: means for selectively connecting a first terminal of the capacitor to the input/output conductor; at least two address conductors of the type where, when a first is energized, the second is invariably at ground potential, the first address conductor being coupled, when energized, to operate the connecting means so as to connect the first terminal of the capacitor to the input/output conductor, the second terminal of the capacitor being connected to the second address conductor so as to ground the second terminal of the capacitor whenever the connecting means is operated.

Claim 30

A memory cell of the capacitive storage type, comprising: a capacitor; an input/output conductor for the capacitor: means for selectively connecting a first terminal of the capacitor to the input/output conductor; at least two address conductors of the type where, when a first is energized, the second is invariably at ground potential, the first address conductor being coupled, when energized, to operate the connecting means so as to connect the first terminal of the capacitor to the input/output conductor, the second terminal of the capacitor being connected to the second address conductor so as to ground the second terminal of the capacitor whenever the connecting means is operated.

Claim 31

A memory circuit comprising a memory cell as recited in claim 11, and further comprising: means connected to the input/output conductor during a writing cycle for selectively charging or discharging the cell capacitor as a function of binary data to be stored in the cell, so that the cell capacitor stores either (1) essentially ground potential or (2) a predetermined charge (VM) of a given polarity at the end of the writing cycle.

Claim 32

A memory circuit as recited in claim 12: wherein the charging or discharging means inverts an input data signal so that the cell capacitor stores the complement of the data signal; further comprising read-out means selectively connectable to the charging or dischArging means during a read cycle; and wherein the charging or discharging means also re-inverts the data stored on the cell capacitor during the read cycle so that the output data is read out from the cell in its original form.

Claim 33

A circuit as recited in claim 13, wherein the charging or discharging means includes a sense/refresh amplifier having a first node connected to the input/output conductor and a second node selectively connectable to data read or write circuits, the data inputs and outputs being connectable only to the second node, the sense/refresh amplifier including means for inverting the input data signal applied at the second node during a read cycle so that the complement appears at the first node and is transmitted to the cell capacitor, and for reinverting at the second node a signal from the cell capacitor at the first node, and transmitting the re-inverted signal to the read circuit during the read cycle.

Claim 34

A memory circuit as recited in claim 12, and further including a circuit for periodically refreshing the signal on the cell capacitor, which comprises: A. a pair of load capacitances of equal value, a first load capacitance being connected to the input/output conductor for the cell capacitor so that, when selected, the cell capacitor is connected in parallel with the first load capacitance at a time t1; B. means for bringing both load capacitances to a common initial potential prior to the time t1; C. means for connecting the load capacitances in parallel to a source of charging potential at the time t1, the source being of the same polarity as said predetermined charge VM and of a higher magnitude than the initial potential so that both load capacitances tend to charge from the source at the same rate, the connection of the cell capacitor to the first load capacitance being such that

Claim 35

In a memory circuit of the type where either (1) essentially ground potential or (2) a predetermined charge (VM) of a given polarity is stored on a memory capacitor as a function of binary data, a circuit for refreshing the signal on the memory capacitor, which comprises: A. a pair of load capacitances of equal value; B. means for bringing both load capacitances to a common initial potential prior to a time t1; C. means for connecting the load capacitances in parallel to a source of charging potential at the time t1, the source being of the same polarity as said predetermined charge VM and of a higher magnitude than the initial potential so that both load capacitances would tend to charge from the source at the same rate; D. means for connecting the memory capacitor in parallel with a first one of the load capacitances at the time t1 so that

Claim 36

In a memory circuit of the type where either (1) essentially ground potential or (2) a predetermined charge (VM) of a given polarity is stored on a memory capacitor as a function of binary data, a circuit for refreshing the signal on the memory capacitor, which comprises: A. a pair of load capacitances of equal value; B. means for bringing both load capacitances to a common initial potential prior to a time t1; C. means for connecting the load capacitances in parallel to a source of charging potential at the time t1, the source being of the same polarity as said predetermined charge VM and of a higher magnitude than the initial potential so that both load capacitances would tend to charge from the source at the same rate; D. means for connecting the memory capacitor in parallel with a first one of the load capacitances at the time t1 so that

Claim 37

A circuit as recited in claim 16, wherein means (B) comprises means for connecting both load capacitances to circuit ground prior to the time t1, ground being the common initial potential, and for removing the ground after t1.

Claim 38

A circuit as recited in claim 17, wherein the ground connecting means comprises: a pair of load resistors connected to the respective load capacitances; and a source of clock pulses connected in parallel to the load resistors and timed so that the clock pulse is at 0 volts prior to time t1 to provide the circuit ground from the clock signal.

Claim 39

A circuit as recited in claim 18, wherein means (C) of claim 16 includes the same load resistors and clock source recited in claim 18, the clock pulse being timed so that it switches to the charging potential at time t1, the clock providing the charging potential required during the cycle for all of the capacitances.

Claim 40

A circuit as recited in claim 19, wherein the load resistors comprise a pair of continuously ON biased field-effect transistors, the transistors serving as load resistors (a) during charging of the load capacitances from the clock voltage after t1, and (b) to ground the load capacitances to the clock ground prior to t1.

Claim 41

A circuit as recited in claim 17, wherein the ground connecting means comprises: a pair of gating devices having first terminals connected to the respective load capacitances and second terminals connected to circuit ground; and a source of clock pulses connected to the gates of the gating devices and timed so as to turn the gating devices ON prior to the time t1 so as to connect load capacitances to circuit ground through the gating devices, and OFF at time t1 so as to isolate the load capacitances from connection to ground through said gating devices.

Claim 42

A circuit as recited in claim 21, wherein means (C) of claim 16 comprises: a pair of load resistors connected to the respective load capacitances; and a constantly ON source of charging potential connected to the load capacitances through the load resistors.

Claim 43

A circuit as recited in claim 22, wherein: the load resistors comprise a pair of continuously ON biased field-effect transistors; and the gating devices comprise a further pair of field-effect transistors having first controlled terminals connected to the respective load capacitances, second controlled terminals connected to circuit ground, and gates coupled to the source of clock pulses.

Claim 44

A circuit as recited in claim 16, wherein means (B) comprises means for bringing both load capacitances to a common relatively low potential VX prior to the time 1, the relatively low potential being less than half of the magnitude of the source of charging potential, so that both load capacitances tend to charge further from VX toward the voltage of the source of charging potential after time t1, when means (C) is actuated.

Claim 45

A circuit as recited in claim 24, wherein: means (E) of claim 16 is further arranged to discharge the slowest charging load capacitor to ground prior to the end of each cycle; the means (B) of claim 24 comprises means for shorting the two load capacitances to each other at a time to corresponding to the start of a cycle and before the next occurrence of time t1, so as to equalize the charges on the load capacitances at VX, and for removing the short at the time t1 to re-isolate the load capacitances for separate charging from the source.

Claim 46

A circuit as recited in claim 25, wherein the means for connecting the load capacitances to each other comprises a gate, and a source of clock signals for turning ON the gate during the time period from to to t1.

Claim 47

A circuit as recited in claim 26, wherein the means (E) of claim 16 includes a pair of voltage sensitive gating means, each having a control element connected to a corresponding one of the load capacitances, and controlled terminals connected between the other load capacitance and circuit ground.

Claim 48

A circuit as recited in claim 16, wherein means (E) further comprises:

Claim 49

A circuit as recited in claim 28, wherein means (1) of claim 28 precludes operation of means (2), and vice versa, so that only a selected one of the load capacitances is fully charged at time t2, the one selected being governed by the charge initially stored on the memory capacitor.

Claim 50

A circuit as recited in claim 29, wherein the circuit ground to which said load capacitances and memory capacitor are selectively discharged is a fixed circuit ground.

Claim 51

A circuit as recited in claim 30, wherein means (1) and (2) of claim 28 comprise cross-coupled voltage-responsive gating devices arranged in a flip-flop configuration so that, when either one first turns ON, it thereafter precludes operation of the other one, the gating devices being connected to the respective load capacitances and being arranged to be turned ON by a predetermined threshold voltage being applied thereto by the prespective load capacitance so as to connect the opposite load capacitance to the circuit ground.

Claim 52

A memory circuit as recited in claim 28, further comprising: means for reading the charge on the second load capacitance after tqme t2, which charge is the complement of the charge on the memory capacitor at the time t2, thus providing that the data is read out in inverted form from the memory capacitor selectively connected to the first load capacitance.

Claim 53

A memory circuit as recited in claim 32, further comprising means for initially storing a signal on the memory capacitor selectively connected to the first load capacitance, which stored signal is the complement of the data being written.

Claim 54

A memory circuit as recited in claim 33, wherein: there are provided an even numbered plurality of memory capacitors arranged in first and second banks having equal numbers of memory capacitors, the memory capacitors in the first bank being slectively aNd individually connectable by connecting means to the first load capacitance, the memory capacitors in the second bank being selectively and individually connectable by additional connecting means to the second load capacitance, the connecting means being arranged so that only one is actuated in any one cycle, the data stored on and read from the second bank of memory capacitors connected to the second load capacitance being stored and read in normal form, not in inverted form.

Claim 55

A memory circuit as recited in claim 34, wherein the means for selectively connecting the memory capacitors in parallel with the associated load capacitance comprises: a first input/output conductor connected at one end to the first load capacitance and connectable to each of the memory capacitors in the first bank; a second input/output conductor connected at one end to the second load capacitance, connectable to each of the memory capacitors in the second bank, and selectively connectable at its other end to the read and write circuits; and address means, including one address conductor associated with each memory capacitor, for connecting one and only one memory capacitor to the associated input/output conductor at the time t1 and for disconnecting the memory capacitor from the input/output conductor at the end of each cycle, prior to the operation of means (B) of claim 16, so as to isolate the signal on the selected memory cell in preparation for further refresh and/or read cycles.

Claim 56

A circuit as recited in claim 35, wherein: the address means is of the type when only one selected address conductor is energized in any one cycle to connect the associated memory capacitor to the corresponding input/output conductor, and all other address conductors are invariably at ground potential; and the terminal of each memory capacitor opposite to the corresponding input/output conductor is connected to an adjacent address conductor so as to provide ground potential on that terminal whenever that memory capacitor is selected.

Claim 57

A read/write memory circuit, comprising: A. means for inverting data signals, having input/output nodes 1 and 2 on opposite sides thereof; B. a first bank of memory cells disposed on a first side of the inverting means, each having a memory storage element; C. a first I/O conductor connected at its inner end to node 1, for connecting the memory storage element of any selected cell in the first bank to node 1, the first I/O conductor being unconnectable to any external circuits at its outer end; D. a second bank of memory cells equal in number to the first bank and disposed on the second side of the inverting means, each having a memory storage element; E. a second I/O conductor connected at its inner end to node 2, for connecting the memory storage element of any selected cell in the second bank to node 2; F. means for selectively connecting the outer end of only the second I/O conductor to external write or read circuits when it is desired to write a bit of data on the memory storage element of any selected cell in either bank, or to read out a data signal from any cell in either bank; G. means for addressing any one selected cell in either bank, to connect the selected memory storage element to its associated I/O conductor; H. the means for inverting being arranged so that:

Claim 58

A read/write memory circuit, comprising: A. means for inverting data signals, having input/output nodes 1 and 2 on opposite sides thereof; B. a first bank of memory cells disposed on a first side of the inverting means, each having a memory storage element; C. a first I/O conductor connected at its inner end to node 1, for connecting the memory storage element of any selected cell in the first bank to node 1, the first I/O conductor being unconnectable to any external circuits at its outer end; D. a second bank of memory cells equal in number to the first bank and disposed on the second side of the inverting means, each having a memory storage element; E. a second I/O conductor connected at its inner end to node 2, for connecting the memory storage element of any selected cell in the second bank to node 2; F. means for selectively connecting the outer end of only the second I/O conductor to external write or read circuits when it is desired to write a bit of data on the memory storage element of any selected cell in either bank, or to read out a data signal from any cell in either bank; G. means for addressing any one selected cell in either bank, to connect the selected memory storage element to its associated I/O conductor; H. the means for inverting being arranged so that:

Claim 59

A memory circuit as recited in claim 37, wherein the inverting means comprises a sense/refresh amplifier circuit, which also functions to refresh the signal stored on any selected memory cell in any cycle where a write operation is not selected.

Claim 60

A memory circuit as recited in claim 38, wherein a single phase clock is provided for operating the sense/refresh amplifier.

Claim 61

A memory circuit as recited in claim 39, wherein: the memory storage elements memory capacitors capable of storing either (b 1) essentially ground potential, or (2) a predetermined charge (VM) as a function of the binary data; and the sense/refresh amplifier comprises: first and second load capacitances of equal value connected respectively to nodes 1 and 2; means actuated by a first signal from the clock for bringing both load capacitances to a common initial potential between cycle times to and t1the initial potential being less than half of a full cell charge VM; means actuated by a second signal from the clock for connecting the load capacitances in parallel to a source of charging potential of the same polarity as VM at time t1, so that both load capacitances would tend to charge at the same rate toward the source potential; means for connecting the selected memory capacitor to its associated node from time t1 to the end of the cycle t''o, so that the load capacitances charge at unequal rates depending on whether the selected memory capacitor has been storing 1. essentially ground potential, or (2) a voltage at or near VM; means for selectively connecting the write circuit to node 2 from prior to time t1 to the end of the cycle data is to be written; means for sensing which load capacitance is charging faster after time t1 and for grounding the slower load capacitance and associated node and memory capacitor if connected, while permitting complete charging of the faster load capacitance and memory capacitor if connected by a cycle time t2, at which time the data has been written or the signal on the selected memory capacitor has been refreshed whenever the write operation is not selected for that memory capacitor; and mean for selectively reading the signal on the second load capacitance after time t2 and before t''o whenever a read operation is selected for the memory cell.

Claim 62

A memory circuit as recited in claim 40, further comprising: a plurality of rows Xl to Xi of memory circuits as recited in claim 40, having their memory capacitors arranged in perpendicular columns Yl to Yj, the second I/O conductors for each cell also comprising access conductors Xl-Xi; a plurality of gating means for connecting only one selected row to either the read or the write circuits; and a plurality of Y access conductors Y1 to Yj, selectively energizable to connect all memory capacitors in one selected column to their associated I/O conductors, all other Y access conductors except a selected one being at ground potential, so that each memory capacitor in the selected column is refreshed during each cycle, except for a memory capacitor in a selected row during a writing cycle.

Claim 63

A circuit as recited in claim 41, wherein each memory capacitor has its terminal opposite to the corresponding I/O conductor connected to an adjacent Y access conductor, so as to provide a common ground signal from the adjacent access conductor on that terminal of all memory capacitors in the selected column.

Claim 64

A memory as recited in claim 37, wherein: the means for addressing includes a plurality of parallel address conductors, one associated with each cell and arranged so that only one selected address conductor is energized in a cycle to select a given memory cell, the remaininG address conductors being at essentially ground potential; and each memory element comprises a cell capacitor having a first terminal connectable by the addressing means to the corresponding I/O conductor and a second terminal connected to an adjacent address conductor.

Claim 65

In a memory system of the type where either (1) essentially ground potential or (2) a predetermined charge (VM) of a given polarity is stored on a memory capacitor as a function of binary data, a method of refreshing the signal on the memory capacitor, which comprises: A. bringing both load capacitances of a pair of load capacitances of equal value to a common initial potential prior to a time t1; B. connecting the load capacitances in parallel to a source of charging potential at the time t1, the source being of the same polarity as said predetermined charge VM and of a higher magnitude than the initial potential so that both load capacitances would tend to charge from the source at the same rate; C. connecting the memory capacitor in parallel with a first one of the load capacitances at the time t1 so that

Claim 66

In a memory system of the type where either (1) essentially ground potential or (2) a predetermined charge (VM) of a given polarity is stored on a memory capacitor as a function of binary data, a method of refreshing the signal on the memory capacitor, which comprises: A. bringing both load capacitances of a pair of load capacitances of equal value to a common initial potential prior to a time t1; B. connecting the load capacitances in parallel to a source of charging potential at the time t1, the source being of the same polarity as said predetermined charge VM and of a higher magnitude than the initial potential so that both load capacitances would tend to charge from the source at the same rate; C. connecting the memory capacitor in parallel with a first one of the load capacitances at the time t1 so that

Claim 67

The method as recited in claim 44, wherein steps (D) and (E) further comprise: discharging the slowest charging load capacitance to ground by a later cycle time t2, while permitting full charging of the faster charging load capacitance, and memory capacitor if connected to it, by the time t2.

Claim 68

A method of operating a memory of the type recited in claim 45, which further comprises: reading the charge on the second load capacitance after time t2, which charge is the complement of the charge on the memory capacitor at the time t2, thus providing that the data is read out in inverted form from the memory capacitor connected to the first load capacitance.

Claim 69

The method as recited in claim 46, further comprising the step of initially storing a signal on the memory capacitor connected to the first load capacitance, which stored signal is the complement of the data being written.

Claim 70

The method as recited in claim 47, for operating a random-access memory of the type having an even numbered array of memory capacitors of the same type, wherein: memory capacitors in a first bank of capacitors are selectively and individually connected to the first load capacitance during selected cycles, and memory capacitors in a second, equal numbered bank are selectively and individually connected to the second load capacitance during other cycles, only one memory capacitor in the entire array being connected to the corresponding load capacitance in any one cycle, the data being stored on and read from the second bank of memory capacitors in normal form, not in inverted form.

Claim 73

A method as recited in claim 49, wherein the reading step is accomplished by sensing the state of a load capacitance connected to the second node after time t2, the load capacitance bearing a signal which is the complement of that stored on a memory cell in the first bank if connected to the first node at time t2, and the same as that stored on a memory cell in the second bank if connected to the second node at time 2.