US4141027A
Expired / Lapsed
US
⏱️ 0.0 years remaining
IGFET integrated circuit memory cell
Assignee: Samsung Electronics Co Ltd
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Filing: 1978-05-19
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Granted: 1979-02-20
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Expires: 1998-05-19
Abstract
Abstract An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps. A subsequent source and drain diffusion causes lateral migration of the conductive portions of the cell to increase the storage capacitance and to insure electrical contact between the island region of the capacitor and the source of the transfer transistor.
Inventors
- 👤 Steven M. Baldwin
- 👤 Donald L. Henderson, Sr.
- 👤 Joel A. Karp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:44
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/30; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/64; H10P30/21; H10P30/212; Y; Y10; Y10S; Y10S148/00; Y10S148/136; Y10T; Y10T29/00; Y10T29/43; Y10T29/435
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
217 words
A semiconductor capacitor comprising: a substrate having a major surface, said substrate being of one conductivity type with a given impurity concentration; a first region of opposite conductivity type inset in said substrate surface, said first region having a surface in the plane of said major surface, an opposite surface and side surfaces at least one of which is provided to make electrical contact; a second region wholly surrounding said first region in said substrate except for said surface in the plane of said major surface and said electrical contact, said second region being of the same conductivity type as said substrate but having a greater impurity concentration than said substrate, said second region and said first region forming a PN junction therebetween; an insulating layer on said substrate surface, said insulating layer having a portion overlaying said first region, which portion has a thickness less than the thickness of other portions of said insulating layer adjacent the overlaying portion; a conductive field plate on said portion overlaying said first region to provide capacitance between said first region and said field plate; and a voltage source coupled to said field plate; wherein said second region restricts the depletion region of said PN junction formed with said first region thereby increasing the total capacitance of said semiconductor capacitor.
Claim 2
Dependent Claim
217 words
A semiconductor capacitor comprising: a substrate having a major surface, said substrate being of one conductivity type with a given impurity concentration; a first region of opposite conductivity type inset in said substrate surface, said first region having a surface in the plane of said major surface, an opposite surface and side surfaces at least one of which is provided to make electrical contact; a second region wholly surrounding said first region in said substrate except for said surface in the plane of said major surface and said electrical contact, said second region being of the same conductivity type as said substrate but having a greater impurity concentration than said substrate, said second region and said first region forming a PN junction therebetween; an insulating layer on said substrate surface, said insulating layer having a portion overlaying said first region, which portion has a thickness less than the thickness of other portions of said insulating layer adjacent the overlaying portion; a conductive field plate on said portion overlaying said first region to provide capacitance between said first region and said field plate; and a voltage source coupled to said field plate; wherein said second region restricts the depletion region of said PN junction formed with said first region thereby increasing the total capacitance of said semiconductor capacitor.
Claim 3
Dependent Claim
26 words
The capacitor of claim 1 wherein said substrate and said second region are of a P-type conductivity and said first region is of an N-type conductivity.
Claim 4
Dependent Claim
56 words
The capacitor of claim 2 wherein the impurity concentration of said substrate is about 10 14 -10 15 atoms/cm 3 , the impurity concentration of said second region is 10 17 -10 18 atoms/cm 3 , and the impurity concentration of said first region is 1 × 10 18 -5 × 10 18 atoms/cm 3 .
Claim 5
Dependent Claim
233 words
A semiconductor integrated circuit structure comprising, in combination: a capacitor including a substrate having a major surface, said substrate being of one conductivity type with a given impurity concentration; a first region of opposite conductivity type inset in said substrate surface, said first region having a surface in the plane of said major surface, an opposite surface and side surfaces at least one of which is provided to make electrical contact; a second region wholly surrounding said first region in said substrate except for said major surface and said electrical contact, said second region being of the same conductivity type as said substrate but having a greater impurity concentration than said substrate, said second region and said first region forming a PN junction therebetween; an insulating layer on said substrate surface, said insulating layer having a portion overlaying said first region, which portion has a thickness less than the thickness of other portions of said insulating layer adjacent to said overlaying portion; a conductive field plate on said portion overlaying said first region to provide a capacitance between said first region and said field plate; and a voltage source coupled to said field plate; and a field effect transistor for transferring electrical charge into and out of said capacitor, said transfer transistor including source, drain, and gate regions, with said source region being in electrical contact with said first region of said capacitor.
Claim 6
Dependent Claim
233 words
A semiconductor integrated circuit structure comprising, in combination: a capacitor including a substrate having a major surface, said substrate being of one conductivity type with a given impurity concentration; a first region of opposite conductivity type inset in said substrate surface, said first region having a surface in the plane of said major surface, an opposite surface and side surfaces at least one of which is provided to make electrical contact; a second region wholly surrounding said first region in said substrate except for said major surface and said electrical contact, said second region being of the same conductivity type as said substrate but having a greater impurity concentration than said substrate, said second region and said first region forming a PN junction therebetween; an insulating layer on said substrate surface, said insulating layer having a portion overlaying said first region, which portion has a thickness less than the thickness of other portions of said insulating layer adjacent to said overlaying portion; a conductive field plate on said portion overlaying said first region to provide a capacitance between said first region and said field plate; and a voltage source coupled to said field plate; and a field effect transistor for transferring electrical charge into and out of said capacitor, said transfer transistor including source, drain, and gate regions, with said source region being in electrical contact with said first region of said capacitor.
Claim 7
Dependent Claim
39 words
Thestructure of claim 4 wherein said substrate and said second region in said capacitor have a P-typeconductivity, with said first region of said capacitor and said source and said drain regions of said transfer transistor being of N-type conductivity.
Claim 8
Dependent Claim
37 words
The structure of claim 5 wherein the impurity concentration of said source region of said transfer transistor is greater than that of said second region, thereby insuring good electrical contact between said capacitor and said transfer transistor.
Claim 9
Dependent Claim
74 words
The structure of claim 6 wherein the impurity concentration of said substrate is about 10 14 -10 15 atoms/cm 3 , the impurity concentration of said second region is about 10 17 -10 18 atoms/cm 3 , the impurity concentration of the first region is about 1 × 10 18 -5 × 10 18 atoms/cm 3 , and the impurity concentration of said source region is about 10 19 -10 20 atoms/cm 3 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-19 | 1982-08-21 | 1983-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-19 | 1986-08-21 | 1987-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-19 | 1990-08-21 | 1991-02-20 | $7700.00 | Window Closed / Lapsed |