US3758831A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor with improved breakdown mode
Assignee: Motorola Solutions Inc
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Filing: 1971-06-07
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Granted: 1973-09-11
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Expires: 1991-06-07
Abstract
Abstract There is disclosed a transistor with improved protection against excessive reverse biasing voltages. The improved protection is the result of providing a punch-through breakdown mode which is operative to the exclusion of an avalanche breakdown mode. In the improved transistor, the punch-through breakdown current is dissipated over a wide area such that little if any structural damage occurs. The provision of a punch-through breakdown to the exclusion of avalanche breakdown is accomplished by reducing the doping concentration in the base of the transistor under the emitter or by decreasing the distance between the collector-base junction and the emitter-base junction. There is further provided means for controlling the beta of the transistor as the distance between the above two junctions and the base doping concentration are reduced to provide for punch-through breakdown. Means are further provided for causing the punch-through breakdown to occur in a region either removed from the active area of the transistor or confined to a small portion of the active area of the transistor so that the punch-through mechanism does not interfere with the normal operation of the transistor. There is therefore separate control over the gain and the breakdown characteristics of the transistor. The punch-through current is made to flow to the emitter of the transistor whereby the punch-through breakdown current is dissipated over the entire emitter.
Inventors
- 👤 L Clark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:08
CPC Classifications
H; H10; H10D; H10D99/00; H10D10/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
268 words
Apparatus for minimizing the vulnerability of a transistor to excess reverse biasing voltages comprising: means for insuring that punch-through breakdown due to depletion spread in said transistor occurs prior to avalanche breakdown anywhere in the bulk of said transistor when an increasing reverse biasing potential is applied between the emitter and collector of said transistor; wherein the impurity concentration N, of the base region of said transistor is reduced and wherein the distance, t, between the emitter-base junction and the collector-base junction of said transistor is reduced such that N.t is less than that number below which punch-through breakdown is insured; including a region functioning as part of the base region of said transistor interposed between portions of the emitter and base regions of said transistor, said interposed regions being of like conductivity to that of said base region and having a higher impurity concentration than that of said base, said interposed region permitting the control of the beta of said transistor when the impurity concentration of said base regiOn is reduced; and wherein said interposed semiconductor region completely surrounds said emitter region, said transitor further including an auxiliary emitter region diffused into said base region and being electrically shorted to said interposed region the doping of the base region under said auxiliary emitter region and the distance between the bottom of said auxiliary emitter and the collector-base junction being such that punch-through occurs in said base region between the collector-base junction and the auxiliary emitter-base junction, the breakdown current being transported through said auxiliary emitter through said interposed region and through the first emitter of said transistor.
Claim 2
Dependent Claim
268 words
Apparatus for minimizing the vulnerability of a transistor to excess reverse biasing voltages comprising: means for insuring that punch-through breakdown due to depletion spread in said transistor occurs prior to avalanche breakdown anywhere in the bulk of said transistor when an increasing reverse biasing potential is applied between the emitter and collector of said transistor; wherein the impurity concentration N, of the base region of said transistor is reduced and wherein the distance, t, between the emitter-base junction and the collector-base junction of said transistor is reduced such that N.t is less than that number below which punch-through breakdown is insured; including a region functioning as part of the base region of said transistor interposed between portions of the emitter and base regions of said transistor, said interposed regions being of like conductivity to that of said base region and having a higher impurity concentration than that of said base, said interposed region permitting the control of the beta of said transistor when the impurity concentration of said base regiOn is reduced; and wherein said interposed semiconductor region completely surrounds said emitter region, said transitor further including an auxiliary emitter region diffused into said base region and being electrically shorted to said interposed region the doping of the base region under said auxiliary emitter region and the distance between the bottom of said auxiliary emitter and the collector-base junction being such that punch-through occurs in said base region between the collector-base junction and the auxiliary emitter-base junction, the breakdown current being transported through said auxiliary emitter through said interposed region and through the first emitter of said transistor.
Claim 3
Dependent Claim
86 words
The apparatus as recited in claim 1 wherein both the original and auxiliary emitters are diffused in one processing step to equal depths, the impurity concentration in the base region under said auxiliary emitter being such as to cause punch-through breakdown at said auxiliary emitter, the average impurity concentration of the portions of said interposed region and the base region under said original emitter being such as to preclude punch-through therat and such as to maintain the current gain of said transistor at a controlled level.
Claim 4
Dependent Claim
50 words
The apparatus as recited in claim 2 wherein said transistor is silicon, wherein the impurity concentration between said auxiliary emitter and said collector is less than 5 X 1012 atoms/cm2 and wherein the average impurity concentration between said original emitter and said collector is greater than 5 X 1012 atoms/cm2.
Claim 5
Dependent Claim
189 words
Apparatus for minimizing the vulnerability of a transistor to excessive reverse biasing voltages comprising: means for insuring that punch-through breakdown due to depletion spread in said transistor occurs prior to avalanche breakdown anywhere in the bulk of said transistor when an increasing reverse biasing potential is applied between the emitter and collector of said transistor; and said means includes an auxiliary emitter region spaced from the original emitter region of said transistor, said auxiliary emitter region extending down into the base region of said transistor a distance greater than that of said original emitter, said auxiliary emitter region being shorted to said base regions such that any punch-through current passes through said auxiliary emitter region to said base region and then to said original emitter region, the distance, t, between the bottom of said auxiliary emitter region and the collector-base junction of said transistor times the impurity concentration N of the base region under said auxiliary emitter region being such as to insure punch-through breakdown at said auxiliary emitter region prior to either punch-through breakdown at said original emitter or avalanche breakdown anywhere in the bulk of said transistor.
Claim 6
Dependent Claim
189 words
Apparatus for minimizing the vulnerability of a transistor to excessive reverse biasing voltages comprising: means for insuring that punch-through breakdown due to depletion spread in said transistor occurs prior to avalanche breakdown anywhere in the bulk of said transistor when an increasing reverse biasing potential is applied between the emitter and collector of said transistor; and said means includes an auxiliary emitter region spaced from the original emitter region of said transistor, said auxiliary emitter region extending down into the base region of said transistor a distance greater than that of said original emitter, said auxiliary emitter region being shorted to said base regions such that any punch-through current passes through said auxiliary emitter region to said base region and then to said original emitter region, the distance, t, between the bottom of said auxiliary emitter region and the collector-base junction of said transistor times the impurity concentration N of the base region under said auxiliary emitter region being such as to insure punch-through breakdown at said auxiliary emitter region prior to either punch-through breakdown at said original emitter or avalanche breakdown anywhere in the bulk of said transistor.
Claim 7
Dependent Claim
24 words
The apparatus as recited in claim 4 wherein said transistor is silicon and wherein said N.t product is less than 5 X 1012 atoms/cm2.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-10 | 1977-03-12 | 1977-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-10 | 1981-03-12 | 1981-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-10 | 1985-03-12 | 1985-09-11 | $7700.00 | Window Closed / Lapsed |