Fabrication methods for the high capacity ram cell

Claim 1

A method of constructing an array capacity memory cells comprising the steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to define a cell area for each cell of said array and several bit line areas which selectively interconnect said cell areas; (b) introducing ions having majority carriers of a first conductivity type throughout said cell areas, thereby forming a shallow ion layer throughout each cell area; (c) introducing ions having majority carriers of a second conductivity type throughout said cell areas at a level lying below said shallow ion layers, thereby forming a deep ion layer throughout each cell area; (d) disposing a first insulating layer on said first surface overlying said cell areas; (e) forming a patterned layer of conductive material on said insulating layer to define a storage gate region partially overlying each of said cell areas and spaced apart from said bit line areas; (f) removing from each of said cell areas, the portions of said shallow ion layer lying between said storage gate regions and said bit line areas, and (g) introducing ions having majority carriers of said first conductivity type, throughout the portion of each cell area lying between said storage gate regions and said bit line areas, at approximately the same depth and concentration as said deep ion layer lying therein.

Claim 2

A method of constructing an array capacity memory cells comprising the steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to define a cell area for each cell of said array and several bit line areas which selectively interconnect said cell areas; (b) introducing ions having majority carriers of a first conductivity type throughout said cell areas, thereby forming a shallow ion layer throughout each cell area; (c) introducing ions having majority carriers of a second conductivity type throughout said cell areas at a level lying below said shallow ion layers, thereby forming a deep ion layer throughout each cell area; (d) disposing a first insulating layer on said first surface overlying said cell areas; (e) forming a patterned layer of conductive material on said insulating layer to define a storage gate region partially overlying each of said cell areas and spaced apart from said bit line areas; (f) removing from each of said cell areas, the portions of said shallow ion layer lying between said storage gate regions and said bit line areas, and (g) introducing ions having majority carriers of said first conductivity type, throughout the portion of each cell area lying between said storage gate regions and said bit line areas, at approximately the same depth and concentration as said deep ion layer lying therein.

Claim 13

A method of constructing an array of high capacity memory cells comprising the steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to define a cell area for each cell of said array and several bit line areas which selectively interconnect said cell areas; (b) disposing a first insulating layer on said first surface overlying said cell areas; (c) forming a patterned layer of conductive material on said first insulating layer to define transfer gate regions overlying a portion of each of said cell areas lying adjacent to said bit line regions; (d) introducing ions having majority carriers of a first conductivity type, throughout the portion of said cell areas not covered by said transfer gate regions, thereby forming a shallow ion layer in each of said cell areas; (e) exposing said substrate to a high temperature atmosphere to diffuse said shallow ion layer laterally and partially under said transfer gate regions and subsequently; (f) introducing ions having majority carriers of a second conductivity type throughout said portions of said cell areas not covered by said transfer gate regions, at a level lying below said shallow ion layers, thereby forming in each cell area deep ion layer lying laterally within said shallow ion layer of that cell area.

Claim 14

A method of constructing an array of high capacity memory cells comprising the steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to define a cell area for each cell of said array and several bit line areas which selectively interconnect said cell areas; (b) disposing a first insulating layer on said first surface overlying said cell areas; (c) forming a patterned layer of conductive material on said first insulating layer to define transfer gate regions overlying a portion of each of said cell areas lying adjacent to said bit line regions; (d) introducing ions having majority carriers of a first conductivity type, throughout the portion of said cell areas not covered by said transfer gate regions, thereby forming a shallow ion layer in each of said cell areas; (e) exposing said substrate to a high temperature atmosphere to diffuse said shallow ion layer laterally and partially under said transfer gate regions and subsequently; (f) introducing ions having majority carriers of a second conductivity type throughout said portions of said cell areas not covered by said transfer gate regions, at a level lying below said shallow ion layers, thereby forming in each cell area deep ion layer lying laterally within said shallow ion layer of that cell area.

Claim 25

A method of constructing an array of high capacity memory cell comprising the steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to define a cell area of each cell of said array and several bit line areas which selectively interconnect said cell areas; (b) introducing ions having majority carriers of a first conductivity type, throughout said cell areas, thereby forming a shallow ion layer throughout each of said cell areas; (c) disposing a first insulating layer on said first surface overlying said cell areas; (d) masking each of said cell areas so as to expose a storage region lying within each of said cell areas and spaced apart from said bit line areas; (e) introducing ions having majority carries of a second conductivity type, into each of said storage regions at a level lying below said shallow ion layers to form a deep ion layer in each of said cell areas; (f) forming a patterned layer of conductive material on said first insulating layer to define a storage gate region overlying each of said storage regions; (g) removing the portion of said shallow ion layers lying between said storage gate regions and said bit line regions.

Claim 26

A method of constructing an array of high capacity memory cell comprising the steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to define a cell area of each cell of said array and several bit line areas which selectively interconnect said cell areas; (b) introducing ions having majority carriers of a first conductivity type, throughout said cell areas, thereby forming a shallow ion layer throughout each of said cell areas; (c) disposing a first insulating layer on said first surface overlying said cell areas; (d) masking each of said cell areas so as to expose a storage region lying within each of said cell areas and spaced apart from said bit line areas; (e) introducing ions having majority carries of a second conductivity type, into each of said storage regions at a level lying below said shallow ion layers to form a deep ion layer in each of said cell areas; (f) forming a patterned layer of conductive material on said first insulating layer to define a storage gate region overlying each of said storage regions; (g) removing the portion of said shallow ion layers lying between said storage gate regions and said bit line regions.

Claim 36

A method of constructing an array of high capacity memory cells comprising the steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to define a cell area for each cell of said array and several bit line areas which selectively interconnect said cell areas; (b) masking each of said cell areas so as to expose a storage region lying therein and spaced apart from said bit line areas; (c) introducing ions, having majority carriers of a first conductivity type, throughout each of said storage regions thereby forming a shallow ion layer in each cell area; (d) masking each of said areas so as to expose said storage regions except in the area lying closest to said spaced apart bit line regions; (e) introducing ions having majority carriers of a second conductivity type, throughout said partially exposed storage regions, and at a level lying below said shallow ion layer lying therein; (f) disposing a first insulating layer on said first surface overlying said cell areas; (g) forming a patterned layer of conductive material on said first insulating layer to define a storage gate region overlying said storage region of each of said cell areas. (h) selectively removing portions of said conductive material to form a storage gate region overlying said storage region of each of said cell areas.

Claim 37

A method of constructing an array of high capacity memory cells comprising the steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to define a cell area for each cell of said array and several bit line areas which selectively interconnect said cell areas; (b) masking each of said cell areas so as to expose a storage region lying therein and spaced apart from said bit line areas; (c) introducing ions, having majority carriers of a first conductivity type, throughout each of said storage regions thereby forming a shallow ion layer in each cell area; (d) masking each of said areas so as to expose said storage regions except in the area lying closest to said spaced apart bit line regions; (e) introducing ions having majority carriers of a second conductivity type, throughout said partially exposed storage regions, and at a level lying below said shallow ion layer lying therein; (f) disposing a first insulating layer on said first surface overlying said cell areas; (g) forming a patterned layer of conductive material on said first insulating layer to define a storage gate region overlying said storage region of each of said cell areas. (h) selectively removing portions of said conductive material to form a storage gate region overlying said storage region of each of said cell areas.

Claim 47

A method of constructing an array of high capacity memory cells comprising steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to efine a cell area for each cell of said array and several bit lines areas which selectively interconnect said cell areas; (b) masking each of said cell areas so as to expose a storage region lying therein and spaced apart from said bit line areas; (c) introducing ions having majority carriers of a first conductivity type, throughout each of said storage regions, thereby forming a shallow ion layer lying therein; (d) introducing ions having majority carriers of a second conductivity type, throughout said storage regions at a level below said shallow ion layer lying therein, thereby forming a deep ion layer in each cell area; (e) disposing a first insulating layer, on said first surface, overlying said cell areas; (f) forming a patterned layer of conductive material on said first insulating layer to define a storage gate region for each of said cell areas lying above said storage regions, and to further define a transfer gate region for each of said cell areas lying between and spaced apart from said storage gate regions and said bit line areas; (g) introducing ions of said first conductivity type into the portion of each of said cell areas lying between said storage gate region and said transfer gate region.

Claim 48

A method of constructing an array of high capacity memory cells comprising steps of: (a) forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which are patterned to efine a cell area for each cell of said array and several bit lines areas which selectively interconnect said cell areas; (b) masking each of said cell areas so as to expose a storage region lying therein and spaced apart from said bit line areas; (c) introducing ions having majority carriers of a first conductivity type, throughout each of said storage regions, thereby forming a shallow ion layer lying therein; (d) introducing ions having majority carriers of a second conductivity type, throughout said storage regions at a level below said shallow ion layer lying therein, thereby forming a deep ion layer in each cell area; (e) disposing a first insulating layer, on said first surface, overlying said cell areas; (f) forming a patterned layer of conductive material on said first insulating layer to define a storage gate region for each of said cell areas lying above said storage regions, and to further define a transfer gate region for each of said cell areas lying between and spaced apart from said storage gate regions and said bit line areas; (g) introducing ions of said first conductivity type into the portion of each of said cell areas lying between said storage gate region and said transfer gate region.