US5818757A
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Analog and multi-level memory with reduced program disturb
Assignee: SanDisk Technologies LLC
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Filing: 1996-07-22
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Granted: 1998-10-06
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Expires: 2016-07-22
Abstract
Abstract Applying a bias voltage to unselected word-lines reduces program disturb of the threshold voltages of unselected memory cells during a write to a non-volatile memory. Applying the bias voltage only to memory cells which have already been written with threshold voltages higher than a minimum value and not to erased (or virgin) memory cells allows the bias voltage to be higher without creating currents through unselected memory cells. Data such as a series of samples representing a continuous analog signal can be recorded by writing to sequential addresses to fill one row in an array with data before writing to the next row. Bias flag circuits in a row decoder of the memory indicate which rows are filled with data and therefore which word-lines should have the bias voltage applied during a write.
Inventors
- 👤 Hock C. So
- 👤 Sau C. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:48
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3427; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C16/08; G11C16/10; G11C27/00; G11C27/005; G11C7/00; G11C7/16; G11C8/00; G11C8/14
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
131 words
A method for writing a data value to a selected memory cell in an array of memory cells, comprising simultaneously: applying a first voltage to a first word-line in the array, wherein memory cells coupled to the first word-line are in states indicating data values previously written to the memory cells; applying a second voltage to a second word-line which is coupled to the selected memory cell, wherein a combination of the second voltage and voltages applied to a source and a drain of the selected memory cell changes the threshold voltage of the selected memory cell toward a state indicating the data value being written; and applying a third voltage to a third word-line in the array, wherein memory cells coupled to the third word-line are in an erased state.
Claim 2
Independent Claim
131 words
A method for writing a data value to a selected memory cell in an array of memory cells, comprising simultaneously: applying a first voltage to a first word-line in the array, wherein memory cells coupled to the first word-line are in states indicating data values previously written to the memory cells; applying a second voltage to a second word-line which is coupled to the selected memory cell, wherein a combination of the second voltage and voltages applied to a source and a drain of the selected memory cell changes the threshold voltage of the selected memory cell toward a state indicating the data value being written; and applying a third voltage to a third word-line in the array, wherein memory cells coupled to the third word-line are in an erased state.
Claim 3
Dependent Claim
25 words
The method of claim 1, wherein the third voltage is less than the first voltage and the first voltage is less than the second voltage.
Claim 4
Dependent Claim
21 words
The method of claim 2, wherein the third voltage is less than threshold voltages of memory cells in the erased state.
Claim 5
Dependent Claim
40 words
The method of claim 2, wherein the threshold voltages of memory cells in the erased state are less than the first voltage, and the threshold voltages of memory cells in states indicating data values are greater than the first voltage.
Claim 6
Dependent Claim
39 words
The method of claim 1, further comprising erasing the array to set the memory cells in the erased state, wherein at least some of memory cells in the erased state have a threshold voltage less than the first voltage.
Claim 7
Dependent Claim
115 words
The method of claim 5, further comprising writing data values to sequential addresses so that each memory cell in one row is written to before memory cells in an adjacent row are written to, wherein: writing one of said data values to a memory cell raises the threshold voltage of the memory cell above the first voltage; applying the first voltage comprises applying the first voltage to each word-line other than the second word-line, if every memory cell coupled to the word-line has been written; and applying the third voltage comprises applying the third voltage to each word-line other than the second word-line, if ever memory cell coupled to the word-line has not been written.
Claim 8
Dependent Claim
36 words
The method of claim 1, wherein the combination of the second voltage and the voltages applied to the source and the drain of the selected memory cell increases the threshold voltage of the selected memory cell.
Claim 9
Dependent Claim
15 words
The method of claim 1, wherein the data value being written is an analog value.
Claim 10
Dependent Claim
18 words
The method of claim 1, wherein the data value being written is from a set of discrete values.
Claim 11
Dependent Claim
132 words
A non-volatile memory, comprising: an array of memory cells, the array including a set of word-lines, wherein each word-line is coupled to control gates of memory cells in a row associated with the word-line; a row selection circuit which generates a signal identifying one of said rows containing one of said memory cells selected for a write operation; and a bias/driver circuit coupled to the row selection circuit and to the word-lines, the bias/driver circuit including means for identifying rows which contain data values, wherein the bias/dryer circuit applies a first voltage to one of said word-lines corresponding to the row identified by the signal from the row selection circuit, applies a second voltage to word-lines corresponding to rows identified as containing data values, and applies a third voltage to other word-lines.
Claim 12
Dependent Claim
132 words
A non-volatile memory, comprising: an array of memory cells, the array including a set of word-lines, wherein each word-line is coupled to control gates of memory cells in a row associated with the word-line; a row selection circuit which generates a signal identifying one of said rows containing one of said memory cells selected for a write operation; and a bias/driver circuit coupled to the row selection circuit and to the word-lines, the bias/driver circuit including means for identifying rows which contain data values, wherein the bias/dryer circuit applies a first voltage to one of said word-lines corresponding to the row identified by the signal from the row selection circuit, applies a second voltage to word-lines corresponding to rows identified as containing data values, and applies a third voltage to other word-lines.
Claim 13
Dependent Claim
38 words
The non-volatile memory of claim 10, further comprising a column decoder coupled to bit-lines in the array, the column decoder applying a programming voltage to a selected bit-line coupled to the memory cell selected for the write operation.
Claim 14
Dependent Claim
22 words
The non-volatile memory of claim 11, further comprising a sequential address generator coupled to the column decoder and the row selection circuit.
Claim 15
Dependent Claim
67 words
The non-volatile memory of claim 10, wherein the means for identifying rows which contain data values comprises a plurality of volatile memory devices which are coupled to the row selection circuit, wherein each memory device is associated with one of the word-lines in the array and a value in the memory device is set when the row selection circuit selects the word-line associated with the memory device.
Claim 16
Dependent Claim
39 words
The non-volatile memory of claim 10, wherein the means for identifying rows which contain data values comprises logic which determines whether a row of memory devices contains data from a row address signal applied to the row selection circuit.
Claim 17
Dependent Claim
41 words
The non-volatile memory of claim 10, wherein in a write operation, the bias/dryer circuit alternates between applying the first voltage and applying a fourth voltage to the word-line corresponding to the row identified by the signal from the row selection circuit.
Claim 18
Dependent Claim
54 words
The non-volatile memory of claim 15, wherein a first voltage is a programming voltage to change the threshold voltage of a selected memory cell corresponding to the row identified by the signal from the row selection circuit, and the fourth voltage is equal to a threshold voltage being written to the selected memory cell.
Claim 19
Dependent Claim
68 words
A row decoder for a non-volatile memory, comprising: a plurality of memory devices; and a plurality of driver circuits, wherein each driver circuit is coupled to a corresponding one of the memory devices and to a corresponding word-line, and each driver circuit applies to the corresponding word-line a voltage which depends on a state of the corresponding memory devices and on whether the word-line is selected or unselected.
Claim 20
Dependent Claim
68 words
A row decoder for a non-volatile memory, comprising: a plurality of memory devices; and a plurality of driver circuits, wherein each driver circuit is coupled to a corresponding one of the memory devices and to a corresponding word-line, and each driver circuit applies to the corresponding word-line a voltage which depends on a state of the corresponding memory devices and on whether the word-line is selected or unselected.
Claim 21
Dependent Claim
15 words
The row decoder of claim 17, wherein each memory device comprises a volatile memory device.
Claim 22
Dependent Claim
13 words
The row decoder of claim 17, wherein each memory device comprises a latch.
Claim 23
Dependent Claim
19 words
The row decoder of claim 17, wherein the plurality of memory devices constitute storage locations in a shift register.
Claim 24
Dependent Claim
51 words
The row decoder of claim 17, further comprising a decoder tree which generates a signal to identify which one of the word-lines is the selected word-line, wherein the decoder tree is coupled to the plurality of memory devices and sets the state of the memory device corresponding to the selected word-line.
Claim 25
Dependent Claim
144 words
The row decoder of claim 17, wherein the plurality of memory devices are connected in series with each memory device, except a last memory device in the series, having a data output terminal coupled to a data input terminal of a memory device following in the series; a first logic circuit having input terminals coupled to the data input and output terminals of the memory devices and output terminals coupled to the plurality of driver circuits, wherein the first logic circuit generates signals which identify the selected word-line; and a second logic circuit having input terminals coupled to the data input and output terminals of the memory devices and output terminals coupled to the plurality of driver circuits, wherein the second logic circuit generates signals which identify whether a bias voltage is applied to respective word-lines when the word-lines are unselected during a write.
Claim 26
Dependent Claim
48 words
The row decoder of claim 22, wherein the first logic circuit comprises a plurality of exclusive OR gates, each exclusive OR gate having first and second input terminals coupled to respectively the data input terminal and the data output terminal of an associated one of the memory devices.
Claim 27
Dependent Claim
26 words
The row decoder of claim 17, wherein the state of each memory device corresponds to either data having already been written or data having been erased.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-05 | 2002-04-06 | 2002-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-05 | 2006-04-06 | 2006-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-05 | 2010-04-06 | 2010-10-06 | $7700.00 | Window Closed / Lapsed |