US5619450A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Drive circuit for flash memory with improved erasability
Assignee: Fujitsu Semiconductor Ltd
•
Filing: 1995-05-15
•
Granted: 1997-04-08
•
Expires: 2015-05-15
Abstract
Abstract The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.
Inventors
- 👤 Tetsuji Takeguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:32
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/816; G11C29/82; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G11C16/04; G11C16/0408; G11C16/0416; G11C16/08; G11C16/10; G11C16/14; G11C16/16; G11C16/30; G11C5/00; G11C5/14; G11C5/145; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/20; H03K19/21; H03K19/215; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356147; H03K3/356165
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
184 words
An internal power switching circuit for a semiconductor memory, comprising: a first n-channel MIS transistor (704) one of whose drain and source electrodes is connected to a first power line (701) and the other of whose drain and source electrodes is connected to a second power line (702); a second p-channel MIS transistor (705) one of whose drain and source electrodes, and whose well are connected to a third power line (703) the voltage (Vpp) of which is higher than the voltage (Vcc) on said first power line (701), and the other of whose drain and source electrodes is connected to a node (n70); and a third p-channel MIS transistor (706) one of whose drain and source electrodes is connected to said node (n70), and the other of whose drain and source electrodes, and whose well are connected to said second power line (702), further including: a fourth n-channel MIS transistor (707) one of whose drain and source electrodes is connected to said third power line (703) and the other of whose drain and source electrodes is connected to said second power line (702).
Claim 2
Dependent Claim
184 words
An internal power switching circuit for a semiconductor memory, comprising: a first n-channel MIS transistor (704) one of whose drain and source electrodes is connected to a first power line (701) and the other of whose drain and source electrodes is connected to a second power line (702); a second p-channel MIS transistor (705) one of whose drain and source electrodes, and whose well are connected to a third power line (703) the voltage (Vpp) of which is higher than the voltage (Vcc) on said first power line (701), and the other of whose drain and source electrodes is connected to a node (n70); and a third p-channel MIS transistor (706) one of whose drain and source electrodes is connected to said node (n70), and the other of whose drain and source electrodes, and whose well are connected to said second power line (702), further including: a fourth n-channel MIS transistor (707) one of whose drain and source electrodes is connected to said third power line (703) and the other of whose drain and source electrodes is connected to said second power line (702).
Claim 3
Dependent Claim
76 words
An internal power switching circuit for a semiconductor memory according to claim 51, wherein; the on or off operations of said first MIS transistor (704) and third MIS transistor.(706) are complementary to each other; and when said third transistor (706) is to be turned on, a fourth MIS transistor (707) is turned on simultaneously with or after the on operation of said third MIS transistor (706), and then said second MIS transistor (705) is turned on.
Claim 4
Dependent Claim
55 words
An internal power switching circuit for a semiconductor memory according to claim 1, wherein the gate voltage of said fourth MIS transistor (707) during on operation is higher than a voltage resulting from the addition of a threshold value of the fourth MIS transistor (707) to the voltage (Vcc) of said first power line (701).
References Cited (Backward Citations)
JPS49126249A
Cited
JPS50140225A
Cited
US4094012A
Cited
US4289982A
Cited
US4443718A
Cited
US4446536A
Cited
US4649521A
Cited
JPS60229300A
Cited
JPS60211699A
Cited
US4774421A
Cited
JPS61186019A
Cited
US4694430A
Cited
US4761764A
Cited
US4804637A
Cited
US4742492A
Cited
US4939558A
Cited
US4956816A
Cited
US4893275A
Cited
US5008856A
Cited
US5175704A
Cited
US5010520A
Cited
US4820941A
Cited
US4862019A
Cited
JPH01273357A
Cited
US4823318A
Cited
US5336952A
Cited
JPH0271499A
Cited
US5265052A
Cited
JPH03203097A
Cited
US4975883A
Cited
US5157280A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |