US5265052A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wordline driver circuit for EEPROM memory cell
Assignee: Texas Instruments Inc
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Filing: 1992-06-29
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Granted: 1993-11-23
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Expires: 2012-06-29
Abstract
Abstract A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising a positive voltage switching circuit, a first isolating transistor, and a second isolating transistor. The positive voltage switching circuit may include an inverter with feedback transistor and a third isolating transistor. In one embodiment, the positive voltage switching circuit is capable of switching up to three positive voltage values and reference voltage to the wordline terminal.
Inventors
- 👤 Sebastiano D'Arrigo
- 👤 Giuliano Imondi
- 👤 Sung-Wei Lin
- 👤 Gill Manzur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:19
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C8/00; G11C8/08
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
178 words
A circuit for applying voltages to a wordline in a floating-gate memory cell array, comprising; a first voltage supply circuit for supplying at least a first voltage to a first node; a second voltage supply circuit for supplying at least a second voltage to a second node; a third voltage supply circuit for selectively supplying a third voltage to the wordline; a switching circuit for selectively coupling one of said first voltage supply circuit and said second voltage supply circuit to an output node, the switching circuit including an inverter having a first transistor and a second transistor with current paths connected in series between said first node and said second node, the output node connected between the current paths of said first transistor and said second transistor; and a first isolating transistor having a current path coupled between said output node and the wordline for isolating the switching circuit from the wordline when said third voltage supply circuit supplies said third voltage to the wordline, said first isolating transistor has a substrate coupled to said first node.
Claim 2
Dependent Claim
178 words
A circuit for applying voltages to a wordline in a floating-gate memory cell array, comprising; a first voltage supply circuit for supplying at least a first voltage to a first node; a second voltage supply circuit for supplying at least a second voltage to a second node; a third voltage supply circuit for selectively supplying a third voltage to the wordline; a switching circuit for selectively coupling one of said first voltage supply circuit and said second voltage supply circuit to an output node, the switching circuit including an inverter having a first transistor and a second transistor with current paths connected in series between said first node and said second node, the output node connected between the current paths of said first transistor and said second transistor; and a first isolating transistor having a current path coupled between said output node and the wordline for isolating the switching circuit from the wordline when said third voltage supply circuit supplies said third voltage to the wordline, said first isolating transistor has a substrate coupled to said first node.
Claim 3
Dependent Claim
20 words
The circuit of claim 1, in which said first voltage and said second voltage are greater than said third voltage.
Claim 4
Dependent Claim
23 words
The circuit of claim 2, in which said first voltage is positive, said second voltage is ground, and said third voltage is negative.
Claim 5
Dependent Claim
40 words
The circuit of claim 1, in which said first voltage supply circuit includes a programming voltage source, a sense voltage source, and a switch for selectively coupling one of said programming voltage source and said sense voltage source to said
Claim 6
Dependent Claim
42 words
The circuit of claim 1, in which said second voltage supply circuit includes a disturb-protect voltage source, a reference voltage source, and a switch for selectively coupling one of said disturb-protect voltage source and said reference voltage source to said second node.
Claim 7
Dependent Claim
35 words
The circuit of claim 1, in which said third voltage supply circuit includes an erase voltage source and a second isolating transistor having a current path coupled between said erase voltage source and the wordline.
Claim 8
Dependent Claim
25 words
The circuit of claim 6, in which said erase voltage source supplies negative voltage pulses when active and has a high impedance when not active.
Claim 9
Dependent Claim
21 words
The circuit of claim 6, in which said second isolating transistor has a control electrode coupled to said erase voltage source.
Claim 10
Dependent Claim
19 words
The circuit of claim 6, in which said second isolating transistor has a substrate coupled to said first node.
Claim 11
Dependent Claim
36 words
The circuit of claim 1, in which said first transistor and said first isolating transistor are of a first conductivity type and said second transistor is of a second conductivity type opposite said first conductivity type.
Claim 12
Dependent Claim
30 words
The circuit of claim 10, in which said first transistor and said first isolating transistor are n-channel field effect transistors and said second transistor is a p-channel field effect transistor.
Claim 13
Dependent Claim
108 words
The circuit of claim 1, in which said first voltage supply circuit includes a programming voltage source, a sense voltage source, and a first switch for selectively coupling one of said programming voltage source and said sense voltage source to said first node; said second voltage supply circuit includes a disturb-protect voltage source, a reference voltage source, and a second switch for selectively coupling one of said disturb-protect voltage source and said reference voltage source to said second node; and said third voltage supply circuit includes an erase voltage source and a second isolating transistor having a current path coupled between said erase voltage source and the wordline.
Claim 14
Dependent Claim
89 words
The circuit of claim 12, further including: a supply voltage source; a signalling voltage source, said signalling voltage source supplying a voltage less than voltages supplied by supply voltage source, said programming voltage source, said sense voltage source, said disturb-protect voltage source, and said reference voltage source and greater than a voltage supplied by said erasing voltage source; and a third switch for selectively coupling one of said supply voltage source, said sense voltage source, and said signalling voltage source to a control electrode of said first isolating transistor.
Claim 15
Dependent Claim
33 words
The circuit of claim 13, further including: a fourth switch for selectively coupling one of said supply voltage source and said reference voltage source to control electrodes of said first and second transistors.
Claim 16
Dependent Claim
30 words
The circuit of claim 14, further including: a third isolating transistor having a current path coupled between said third switch and said control electrodes of said first and second transistors.
Claim 17
Dependent Claim
100 words
The circuit of claim 14, in which said programming voltage source supplies a voltage in the range of +12 to +16 volts, said sense voltage source supplies a voltage of approximately +3 volts, said disturb-protect voltage source supplies a voltage in the range of +6 to +8 volts, said reference voltage source supplies ground potential, said erase voltage source supplies a voltage in the range -12 to -14 volts, said supply voltage source supplies a voltage in the range of +4 to +6 volts, and said signalling voltage source supplies a voltage in the range of -3 to -5 volts.
Claim 18
Dependent Claim
26 words
The circuit of claim 16, in which said first transistor, said first isolating transistor, and said second isolating transistor have substrates coupled to said first node.
Claim 19
Dependent Claim
37 words
The circuit of claim 1, further including: a feedback transistor having a current path coupled between said first node and control electrodes of said first and second transistors and a control electrode coupled to said output node.
Claim 20
Dependent Claim
18 words
The circuit of claim 18, in which said feedback transistor has a substrate coupled to said first node.
References Cited (Backward Citations)
US4499388A
Cited
US4565932A
Cited
US4733375A
Cited
US4737936A
Cited
US4720816A
Cited
US4694430A
Cited
US4761764A
Cited
US4742492A
Cited
US4893275A
Cited
US5136541A
Cited
US4823318A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-22 | 1997-05-24 | 1997-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-22 | 2001-05-24 | 2001-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-22 | 2005-05-24 | 2005-11-23 | $7700.00 | Window Closed / Lapsed |