Programmable read only memory using stacked-gate cell erasable by hole injection

Claim 2

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including: a semiconductor region; source and drain regions formed in said semiconductor region; a channel region formed between said source and drain regions; a floating gate formed above said channel region; a first insulating layer disposed between said channel region and said floating gate; a control gate formed above said floating gate; a second insulating layer disposed between said floating gate and said control gate; means for applying a positive voltage to said control gate for injecting electrons in said floating gate for writing and applying a negative voltage to said control gate for injecting holes in said floating gate for erasure; and wherein during erasure said means applies a negative voltage for a control gate of a selected memory cell and a positive voltage for respective control gates of each memory cell which is not selected.

Claim 3

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including: a semiconductor region; source and drain regions formed in said semiconductor region; a channel region formed between said source and drain regions; a floating gate formed above said channel region; a first insulating layer disposed between said channel region and said floating gate; a control gate formed above said floating gate; a second insulating layer disposed between said floating gate and said control gate; means for applying a positive voltage to said control gate for injecting electrons in said floating gate for writing and applying a negative voltage to said control gate for injecting holes in said floating gate for erasure; and wherein said control gates of respective memory cells are connected to a word line decoder via a plurality of word lines, and said means sets a LOW level for selected ones of said word lines, and a HIGH level for said word lines which are not selected, and subsequently applies said negative voltage for erasing to said word lines at said LOW level.

Claim 4

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including: a semiconductor region; source and drain regions formed in said semiconductor region; a channel region formed between said source and drain regions; a floating gate formed above said channel region; a first insulating layer disposed between said channel region and said floating gate; a control gate formed above said floating gate; a second insulating layer disposed between said floating gate and said control gate; means for applying a positive voltage to said control gate for injecting electrons in said floating gate for writing and applying a negative voltage to said control gate for injecting holes in said floating gate for erasure; and wherein said control gates of respective memory cells are connected to a word line decoder via a plurality of word lines, and said means sets a LOW level for selected ones of said word lines, and a HIGH level for said word lines which are not selected, and subsequently applies said negative voltage for erasing to said word lines at said LOW level.

Claim 5

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including: a semiconductor region; source and drain regions formed in said semiconductor region; a channel region formed between said source and drain regions; a floating gate formed above said channel region; a first insulating layer disposed between said channel region and said floating gate; a control gate formed above said floating gate; a second insulating layer disposed between said floating gate and said control gate; means for applying a positive voltage to said control gate for injecting electrons in said floating gate for writing and applying a negative voltage to said control gate for injecting holes in said floating gate for erasure; and wherein said control gates of respective memory cells are connected to a word line decoder via a plurality of word lines, and said means latches outputs of said word line decoder, sets levels of all of said plurality of word lines at LOW level, and subsequently applies said negative voltage for erasing to selected ones of said plurality of word lines at said LOW level.

Claim 6

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including: a semiconductor region; source and drain regions formed in said semiconductor region; a channel region formed between said source and drain regions; a floating gate formed above said channel region; a first insulating layer disposed between said channel region and said floating gate; a control gate formed above said floating gate; a second insulating layer disposed between said floating gate and said control gate; means for applying a positive voltage to said control gate for injecting electrons in said floating gate for writing and applying a negative voltage to said control gate for injecting holes in said floating gate for erasure; and wherein said control gates of respective memory cells are connected to a word line decoder via a plurality of word lines, and said means latches outputs of said word line decoder, sets levels of all of said plurality of word lines at LOW level, and subsequently applies said negative voltage for erasing to selected ones of said plurality of word lines at said LOW level.

Claim 7

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region defining therein a source region, a drain region and a channel region defined between said source and drain regions, a floating gate formed above said channel region and insulated therefrom, and a control gate formed above said floating gate and insulated therefrom and each memory cell being designed for writing in a bit data by injecting electrons in said floating gate; and means for applying a erasure voltage to said control gate for lowering a gate junction breakdown voltage at a junction between said semiconductor region and said drain region, and applying a drain voltage for causing breakdown at said junction so as to inject holes in said floating gate for erasure; wherein during erasure said means applies negative voltage for a control gate of selected memory cell and positive voltage for a control gate of a memory cell which is not selected.

Claim 8

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region defining therein a source region, a drain region and a channel region defined between said source and drain regions, a floating gate formed above said channel region and insulated therefrom, and a control gate formed above said floating gate and insulated therefrom and each memory cell being designed for writing in a bit data by injecting electrons in said floating gate; and means for applying a erasure voltage to said control gate for lowering a gate junction breakdown voltage at a junction between said semiconductor region and said drain region, and applying a drain voltage for causing breakdown at said junction so as to inject holes in said floating gate for erasure; wherein during erasure said means applies negative voltage for a control gate of selected memory cell and positive voltage for a control gate of a memory cell which is not selected.

Claim 9

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region defining therein a source region, a drain region and a channel region defined between said source and drain regions, a floating gate formed above said channel region and insulated therefrom, and a control gate formed above said floating gate and insulated therefrom, and each memory cell being designed for writing in a bit data by injecting electrons in said floating gate; and means for applying a erasure voltage to said control gate for lowering a gate junction breakdown voltage at a junction between said semiconductor region and said drain region, and applying a drain voltage for causing breakdown at said junction so as to inject holes in said floating gate for erasure; wherein during erasure said means applies negative voltage for a control gate of a selected memory cell and positive voltage for a control gate of a memory cell which is not selected; and wherein said control gates of respective memory cells are connected to a word line decoder via a plurality of word lines, and said means sets a LOW level for selected ones of said word lines, and a HIGH level for said word lines which are not selected, and subsequently applies said negative voltage for erasing to said word lines at said LOW level.

Claim 10

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region defining therein a source region, a drain region and a channel region defined between said source and drain regions, a floating gate formed above said channel region and insulated therefrom, and a control gate formed above said floating gate and insulated therefrom, and each memory cell being designed for writing in a bit data by injecting electrons in said floating gate; and means for applying a erasure voltage to said control gate for lowering a gate junction breakdown voltage at a junction between said semiconductor region and said drain region, and applying a drain voltage for causing breakdown at said junction so as to inject holes in said floating gate for erasure; wherein during erasure said means applies negative voltage for a control gate of a selected memory cell and positive voltage for a control gate of a memory cell which is not selected; and wherein said control gates of respective memory cells are connected to a word line decoder via a plurality of word lines, and said means sets a LOW level for selected ones of said word lines, and a HIGH level for said word lines which are not selected, and subsequently applies said negative voltage for erasing to said word lines at said LOW level.

Claim 11

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region defining therein a source region, a drain region and a channel region defined between said source and drain regions, a floating gate formed above said channel region and insulated therefrom, and a control gate formed above said floating gate and insulated therefrom, and each memory cell being designed for writing in a bit data by injecting electrons in said floating gate; and means for applying a erasure voltage to said control gate for lowering a gate junction breakdown voltage at a junction between said semiconductor region and said drain region, and applying a drain voltage for causing breakdown at said junction so as to inject holes in said floating gate for erasure; wherein during erasure said means applies negative voltage for a control gate of a selected memory cell and positive voltage for a control gate of a memory cell which is not selected; and wherein said control gates of respective memory cells are connected to a word line decoder via a plurality of word lines, and said means latches outputs of said word line decoder, sets levels of all of said word lines at LOW level, and subsequently applies said negative voltage for erasing to selected ones of said word lines at said LOW level.

Claim 12

An erasable programmable nonvolatile memory device comprising: a plurality of memory cells, each memory cell including a semiconductor region defining therein a source region, a drain region and a channel region defined between said source and drain regions, a floating gate formed above said channel region and insulated therefrom, and a control gate formed above said floating gate and insulated therefrom, and each memory cell being designed for writing in a bit data by injecting electrons in said floating gate; and means for applying a erasure voltage to said control gate for lowering a gate junction breakdown voltage at a junction between said semiconductor region and said drain region, and applying a drain voltage for causing breakdown at said junction so as to inject holes in said floating gate for erasure; wherein during erasure said means applies negative voltage for a control gate of a selected memory cell and positive voltage for a control gate of a memory cell which is not selected; and wherein said control gates of respective memory cells are connected to a word line decoder via a plurality of word lines, and said means latches outputs of said word line decoder, sets levels of all of said word lines at LOW level, and subsequently applies said negative voltage for erasing to selected ones of said word lines at said LOW level.