EP0108681A2
Expired / Lapsed
EP
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Bit erasable electrically erasable programmable read only memory
Assignee: Fairchild Semiconductor Corp
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Filing: 1983-10-27
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Granted: —
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Expires: 2003-10-27
Abstract
Abstract A bit erasable EEPROM is constructed which alleviates the problems of early termination of erasure and over-erasure. Rather than erasing the entire array at once, and thereby causing the problem of early termination of erasure and over-erasure, each cell is erased individually. In another embodiment of this invention, a group of one or more cells on a word line are erased at once with self-termination of the erase operation of each cell occurring when that cell's transistor becomes conductive, and at that time the erasure of only that cell ceases. The erasure of a particular cell ceases without effecting the erasure of operation of other cells. Therefore, the electrical erasure is self-limiting for each individual cell. In another embodiment of this invention, a group of one or more cells on a bit line are erased at once with no danger of under or over-erasure of each particular cell.
Inventors
- 👤 Andrew C. Tickle
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 21:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/04; G11C16/0408; G11C16/0416; G11C16/16
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
191 words
A memory device comprising a plurality of N x M cells (1-1 to N-M), each cell capable of storing a single bit, said device comprising : a plurality of N word lines (203-1 to 203-N); a plurality of M bit lines (202-1 to 202-M); a plurality of M erase lines (201-1 to 201-M); wherein each said cell is associated with one of said plurality of N word lines, one of said plurality of M bit lines, and one of said plurality of M erase lines; characterized in that at least one selected cell is erased by selecting the bit line associated with said at least one selected cell and de-selecting the remaining bit lines, selecting the word line associated with said at least one selected cell and de-selecting the remaining word lines, and applying a plurality of erase pulses to the erase line associated with said at least one selected cell, and in that the contents of each said selected cell is read after each of said plurality of erase pulses, and erasure of said each selected cell is stopped when the contents of said each selected cell has been erased.
Claim 2
Dependent Claim
191 words
A memory device comprising a plurality of N x M cells (1-1 to N-M), each cell capable of storing a single bit, said device comprising : a plurality of N word lines (203-1 to 203-N); a plurality of M bit lines (202-1 to 202-M); a plurality of M erase lines (201-1 to 201-M); wherein each said cell is associated with one of said plurality of N word lines, one of said plurality of M bit lines, and one of said plurality of M erase lines; characterized in that at least one selected cell is erased by selecting the bit line associated with said at least one selected cell and de-selecting the remaining bit lines, selecting the word line associated with said at least one selected cell and de-selecting the remaining word lines, and applying a plurality of erase pulses to the erase line associated with said at least one selected cell, and in that the contents of each said selected cell is read after each of said plurality of erase pulses, and erasure of said each selected cell is stopped when the contents of said each selected cell has been erased.
Claim 3
Dependent Claim
54 words
The structure as in Claim 1, characterized in that each said cell comprises : a drain connected to its associated bit line (202); a source connected to a reference potential; a floating gate; a control gate connected to its associated word line (203) and; an erase terminal connected to its associated erase line (201).
Claim 4
Dependent Claim
58 words
The structure as in Claim 1 or 2, characterized in that, during erasure, said word lines (203) are selected by the application of a low voltage and deselected by the application of a high voltage; and said bit lines (202) are selected by the application of a high voltage, and deselected by the application of a low voltage.
Claim 5
Dependent Claim
33 words
The structure as in anyone of claims 1 to 3, characterized in that said plurality of erase pulses are also applied to the bit line associated with said at least one selected cell.
Claim 6
Dependent Claim
53 words
The structure as in any one of claims 1 to 4, characterized in that one selected cell is erased at a time, and in that the erasure of said selected cell is stopped by terminating the application of said plurality of erase pulses when the content of said selected cell has been erased.
Claim 7
Dependent Claim
84 words
The structure as in any one of claims 1 to 4, characterized in that a plurality of cells associated with a specified word line are erased simultaneously and in that the erasure of each selected cell is stopped when said each selected cell has been erased by preventing said erase pulses to be applied to the erase line associated with said each erased selected cell, whereby the erasure of each erased selected cell ceases without ceasing further erasure of the remaining cells being erased.
Claim 8
Dependent Claim
77 words
The structure as in any one of claims 1 to 4, characterized in that a plurality of cells associated with a specified bit line are erased simultaneously, and in that the erasure of each selected cell is stopped when said each selected cell has been erased by deselecting the word line associated with said each erased selected cell, whereby the erasure of each erased selected cell ceases without ceasing further erasure of the remaining cells being erased.
References Cited (Backward Citations)
No citation records indexed.
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