Electrically erasable programmable read-only memory

Claim 3

The method according to claim 1 characterized by following steps for reading binary data from said electrically erasable programmable read-only memory: (a) applying a read voltage to a selected word line, said read voltage being greater than said low thereshold voltage and less than said high threshold voltage, and, simulataneously, maintaining unselected word lines at zero potential, applying a small potential to selected of said bit lines and maintaining unselected bit lines at zero potential such that a said transistor connected to said selected of said bit lines and having a charged floating gate is nonconducting and a said transistor connected to said selected of said bit lines and having discharged floating gate is conducting; and (b) monitoring whether selected of said transistors is conducting or nonconducting.

Claim 4

The method according to claim 1 or 2 characterized in that each of said memory cells consists of a single floating gate field effect transistor.

Claim 5

The method according to claim 2 or 3 characterized in that each of said memory cells consists of a single n-type floating gate field effect transistor.

Claim 6

The method according to claim 4 characterized in that said erase voltage is about +18.0 volts.

Claim 7

The method according to claim 4 or 5 characterized in that said inhibit voltage is about +12.0 volts.

Claim 8

The method according to claim 4, 5 or 6 characterized in that said write voltage is about +12.0 volts.

Claim 11

The method according to claim 9 characterized in that said insulating material is silicon dioxide.

Claim 12

The method according to claim 9 or 10 characterized in that said first electrically conducting layer is a refractory metal.

Claim 13

The method according to claim 11 characterized in that said refractory metal is molybdenum.

Claim 14

An electrically erasable programmable read-only memory characterized by: (a) a memory array comprising (i)<L matrix of memory cells formed as a plurality of rows and a plurality of columns of said cells, each of said cells utilizing a floating gate field effect transistor for storage of binary data; (ii) a plurality of word lines, the control gate of each said transistor in a row of said memory cells being connected to a word line corresponding to said row; (iii) a plurality of bit lines, the drain of each said transistor in a column of said memory cells being connected to a bit line corresponding to said column; and (iv) a plurality of source lines, the source of each said transistor in a column of said memory cells being connected to a source line corresponding to said column; (b) means for applying an erase voltage to a selected word line and, simultaneously, maintaining unselected word lines as well as all bit lines and all source lines at zero potential such that the floating gate of each said transistor connected to said selected word line is charged to a high threshold voltage; (c) means for maintaining a selected word line at zero potential and, simultaneously, applying an inhibit voltage which is less than said erase voltage to unselected word lines, applying a write voltage to selected of said bit lines and maintaining unselected bit lines at zero potential such that the floating gate of each said transistor having its drain connected to said selected of said bit lines discharges to a low threshold voltage; (d) means for applying a read voltage to a selected word line, said read voltage being greater than said low threshold voltage and less than said high threshold voltage, and, simultaneously, maintaining unselected word lines at zero potential, applying a small potential to selected of said bit lines and maintaining unselected bit lines at zero potential such that a said transistor connected to said selected of said bit lines and having a charged floating gate is nonconducting and a said transistor connected to said selected of said bit lines and having a discharged floating gate is conducting; and (e) means for monitoring whether a selected of said transistors in said matrix is conducting or nonconducting.

Claim 15

An electrically erasable programmable read-only memory characterized by: (a) a memory array comprising (i)<L matrix of memory cells formed as a plurality of rows and a plurality of columns of said cells, each of said cells utilizing a floating gate field effect transistor for storage of binary data; (ii) a plurality of word lines, the control gate of each said transistor in a row of said memory cells being connected to a word line corresponding to said row; (iii) a plurality of bit lines, the drain of each said transistor in a column of said memory cells being connected to a bit line corresponding to said column; and (iv) a plurality of source lines, the source of each said transistor in a column of said memory cells being connected to a source line corresponding to said column; (b) means for applying an erase voltage to a selected word line and, simultaneously, maintaining unselected word lines as well as all bit lines and all source lines at zero potential such that the floating gate of each said transistor connected to said selected word line is charged to a high threshold voltage; (c) means for maintaining a selected word line at zero potential and, simultaneously, applying an inhibit voltage which is less than said erase voltage to unselected word lines, applying a write voltage to selected of said bit lines and maintaining unselected bit lines at zero potential such that the floating gate of each said transistor having its drain connected to said selected of said bit lines discharges to a low threshold voltage; (d) means for applying a read voltage to a selected word line, said read voltage being greater than said low threshold voltage and less than said high threshold voltage, and, simultaneously, maintaining unselected word lines at zero potential, applying a small potential to selected of said bit lines and maintaining unselected bit lines at zero potential such that a said transistor connected to said selected of said bit lines and having a charged floating gate is nonconducting and a said transistor connected to said selected of said bit lines and having a discharged floating gate is conducting; and (e) means for monitoring whether a selected of said transistors in said matrix is conducting or nonconducting.

Claim 16

The memory of claim 13 characterized in that each of said memory cells consists of a single floating gater field effect transistor.

Claim 17

The memory of claim 13 or 14 characterized in that said single floating gate field effect transistor is an n-'type transistor.

Claim 18

The memory of claim 13 or 14 characterized in that said single floating gate field effect transistor is a p-type transistor.

Claim 19

The memory of any one of claims 13-16 characterized in that each of said memory cells consists of a composite floating gate field effect transistor, said composite transistor comprising: (a) first and second semiconductor regions of a first conductivity type, said first and second regions being physically separated by a third semiconductor region of a second conductivity type, a selected of said bit lines and a selected of said source lines being connected to said first and second regions, respectively; (b) a first electrically conducting layer overlying said third region and at least a portion of said second region and separated from said first, second and third regions by an electrically insulating material, a portion of said insulating material between said first conducting layer and said second region being about 200 Angstroms or less thick; and (c) a second electrically conducting layer overlying said first conducting layer and also overlying the entire of said third region, said second conducting layer being separated from said first conducting layer and from said first, second and third regions by said insulating material.

Claim 20

The memory of claim 17 characterized in that said insulating material is silicon dioxide.

Claim 21

The memory of claims 17 or 18 characterized in that said first electrically conducting layer is a refractory metal.

Claim 22

The memory of claim 19 characterized in that said refractory metal is molybdenum.

Claim 23

The memory of any one of claims 13-20 characterized in that said small potential is sufficiently small to prevent long-term weak writing.

Claim 24

The memory of claim 21 characterized in that said small potential is about 2.0 volts.

Claim 25

The memory of any one of claims 13-22 characterized in that said means for applying an erase voltage comprises a row address decoder having a plurality of output lines, individual of said output lines being connected to a corresponding of said word lines; said means for applying a write potential to said bit lines comprises a column address decoder having a pluralitv of output lines, individual of said output lines being connected to a corresponding of said bit lines; and said means for monitoring comprises an input/output buffer connected to said memory array for determining whether selected of said memory cells of said array are conducting or nonconducting.

Claim 26

The memory of claim 23 characterized in that said row address decoder is a dynamic decoder.

Claim 27

The memory of claim 23 characterized in that said row address decoder is a static decoder.

Claim 28

The memory of claims 23, 24 or 25 characterized in that each of said memory cells consists of a single floating gate field effect transistor.

Claim 29

The memory of anv one of claims 13-26 chartacterized in that said applied voltages are positive.

Claim 30

A decoder having a plurality of output lines, characterized by: (a) means for directing a first voltage to a selected output line while simultaneously maintaining unselected output lines at zero potential; (b) means for maintaining a selected output line at zero potential and simultaneously directing a second voltage which is less than said first voltage to unselected output lines; and (c) means for directing a third voltage to a selected output line and simultaneously maintaining unselected output lines at zero potential.

Claim 31

A decoder having a plurality of output lines, characterized by: (a) means for directing a first voltage to a selected output line while simultaneously maintaining unselected output lines at zero potential; (b) means for maintaining a selected output line at zero potential and simultaneously directing a second voltage which is less than said first voltage to unselected output lines; and (c) means for directing a third voltage to a selected output line and simultaneously maintaining unselected output lines at zero potential.

Claim 32

The decoder of claim 28 characterized in that said decoder is a dynamic decoder.

Claim 33

The decoder of claim 28 characterized in that said decoder is a static decoder.

Claim 36

The method of claim 31 characterized in that said predetermined amount is about 0.5 volts.

Claim 37

A composite floating gate field effect transistor, characterized by: (a) first and second semiconductor regions of a first conductivity type, said first and second regions being physically separated by a third semiconductor region of a second conductivity type; (b) a first electrically conducting layer overlying said third region and at least a portion of said second region and separated from said first, second and third regions by an electrically insulating material, a portion of said insulating material between said first conducting layer and said second region being about 200 Angstroms or less thick; and (c) a second electrically conducting layer overlying said first conducting layer and also overlying said third region, said second conducting layer being separated from said first conducting layer and from said first, second and third regions by said insulating material..

Claim 38

A composite floating gate field effect transistor, characterized by: (a) first and second semiconductor regions of a first conductivity type, said first and second regions being physically separated by a third semiconductor region of a second conductivity type; (b) a first electrically conducting layer overlying said third region and at least a portion of said second region and separated from said first, second and third regions by an electrically insulating material, a portion of said insulating material between said first conducting layer and said second region being about 200 Angstroms or less thick; and (c) a second electrically conducting layer overlying said first conducting layer and also overlying said third region, said second conducting layer being separated from said first conducting layer and from said first, second and third regions by said insulating material..

Claim 39

The transistor of claim 33 characterized in that said insulating material is silicon dioxide.

Claim 40

The transistor of claims 33 or 34 characterized in that said first electrically conducting layer is a refractory metal.

Claim 41

The transistor of claim 35 characterized in that said refractory metal is molybdenum.

Claim 42

The transistor of any one of claims 33-37 characterized in that said first and second regions comprise n-type semiconductor material and said third region comprises p-type semiconductor.