EP0209912A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1986-07-24
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Granted: —
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Expires: 2006-07-24
Abstract
Abstract Using a comparatively low supply voltage of, e.g., +5 V and a minus great voltage, the voltage difference between the gate (7) of an MNOS transistor and a P-type well region (2) in which the MNOS transistor is formed is relatively changed to execute the writing and erasing of the MNOS transistor. Thus, the potential of an N-type semiconductor substrate (1) can be fixed to a comparatively low potential, e.g., about +5 V, so that a P-channel MOSFET formed on the semiconductor substrate (1) operates with an ordinary signal level. Consequently, an EEPROM whose peripheral circuits are constructed of CMOS circuits can be provided. Accordingly, reduction in the power consumption of the EEPROM can be attained.
Inventors
- 👤 Kazunori Furusawa
- 👤 Shinji Nabetani
- 👤 Yoshiaki Kamigaki
- 👤 Masaaki Terasawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 15:57
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/04; G11C16/0466; G11C16/10; G11C16/12; G11C16/14
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
119 words
A semiconductor memory device comprising: a semiconductor substrate (1) which has one majore surface, a region (2) of a first conductivity type which extends to a part of said major surface, a plurality of memory cells (M) which are formed in the first conductivity type region (2), and peripheral circuits which are formed in the other part of said major surface in relation to said plurality of memory cells (M), wherein said each memory cell (M) includes a non-volatile storage element which can electrically write and erase data, and said each peripheral circuit is constructed of a complementary MIS type circuit (Ql,Q2, ...) which includes a series circuit consisting of a P-channel MISFET and an N-channel MISFET. (Fig. 2)
Claim 2
Dependent Claim
119 words
A semiconductor memory device comprising: a semiconductor substrate (1) which has one majore surface, a region (2) of a first conductivity type which extends to a part of said major surface, a plurality of memory cells (M) which are formed in the first conductivity type region (2), and peripheral circuits which are formed in the other part of said major surface in relation to said plurality of memory cells (M), wherein said each memory cell (M) includes a non-volatile storage element which can electrically write and erase data, and said each peripheral circuit is constructed of a complementary MIS type circuit (Ql,Q2, ...) which includes a series circuit consisting of a P-channel MISFET and an N-channel MISFET. (Fig. 2)
Claim 3
Dependent Claim
23 words
The device of claim 1, wherein said semiconductor substrate (1) has an N-conductivity type, and said first conductivity type is a P-conductivity type.
Claim 4
Dependent Claim
15 words
The device of claim 2, wherein said non-volatile storage element (M) includes an MNOS transistor.
Claim 5
Dependent Claim
97 words
The device of claim 3, wherein when data is to be written into said MNOS transistor, a plus voltage is applied to a gate electrode (7) of said MNOS transistor and a minus voltage is applied to said first conductivity type region (2); when data is to be erased, a minus voltage is applied to said gate electrode (7) of said MNOS transistor and a plus voltage is applied to said first conductivity type region (2); and in the writing and erasing modes, a fixed plus voltage is applied to said semiconductor substrate (1). (Figs. lA, 1B)
Claim 6
Dependent Claim
110 words
A semiconductor memory device comprising: a plurality of memory cells (M) which are formed within a well region (2) of a second conductivity type provided in a part of a semiconductor substrate (1) of a first conductivity type, and peripheral circuits which are formed in the other part of the first conductivity type semiconductor substrate (1) in relation to said plurality of memory cells (M), wherein said each memory cell (M) is constructed of a single MNOS transistor, and said each peripheral circuit is constructed of a complementary MIS type circuit (Q1, Q2, ...) which includes a series circuit consisting of a P-channel MISFET and an N-channel MISFET. (Fig. 2)
Claim 7
Dependent Claim
110 words
A semiconductor memory device comprising: a plurality of memory cells (M) which are formed within a well region (2) of a second conductivity type provided in a part of a semiconductor substrate (1) of a first conductivity type, and peripheral circuits which are formed in the other part of the first conductivity type semiconductor substrate (1) in relation to said plurality of memory cells (M), wherein said each memory cell (M) is constructed of a single MNOS transistor, and said each peripheral circuit is constructed of a complementary MIS type circuit (Q1, Q2, ...) which includes a series circuit consisting of a P-channel MISFET and an N-channel MISFET. (Fig. 2)
Claim 8
Dependent Claim
24 words
A semiconductor memory device according to claim 5, wherein said first conductivity type is an N-type, and said second conductivity type is a P-type.
Claim 9
Dependent Claim
40 words
The device of claim 6, wherein said peripheral circuits include a voltage conversion circuit (XDRV) which forms a plus, minus or ground ptential for causing said MNOS transistor to perform an operation of writing, erasing or reading data. (Fig. 2)
Claim 10
Dependent Claim
134 words
A semiconductor memory device comprising: a plurality of memory cells which are formed within a well region (2) of a second conductivity type provided in a part of a semiconductor substrate (1) of a first conductivity type, and peripheral circuits which are formed in the other part of the first conductivity type semiconductor substrate (1) in relation to said plurality of memory cells, wherein said each memory cell is constructed of a single MNOS transistor (Q2'), an addressing MOSFET (Q1') disposed on a drain side of said MNOS transistor (Q2'), and an isolating MOSFET (Q3') disposed on a source side of said MNOS transistor (Q2'), and said each peripheral circuit is constructed of a complementary MIS type circuit which includes a series circuit consisting of a P-channel MISFET and an N-channel MISFET. (Fig. 4)
Claim 11
Dependent Claim
134 words
A semiconductor memory device comprising: a plurality of memory cells which are formed within a well region (2) of a second conductivity type provided in a part of a semiconductor substrate (1) of a first conductivity type, and peripheral circuits which are formed in the other part of the first conductivity type semiconductor substrate (1) in relation to said plurality of memory cells, wherein said each memory cell is constructed of a single MNOS transistor (Q2'), an addressing MOSFET (Q1') disposed on a drain side of said MNOS transistor (Q2'), and an isolating MOSFET (Q3') disposed on a source side of said MNOS transistor (Q2'), and said each peripheral circuit is constructed of a complementary MIS type circuit which includes a series circuit consisting of a P-channel MISFET and an N-channel MISFET. (Fig. 4)
Claim 12
Dependent Claim
21 words
The device of claim 8, wherein said first conductivity type is an N-type, and said second conductivity type is a P-type.
Claim 13
Dependent Claim
62 words
The device of claim 9, further comprising a common source line (CS) to which said isolating MOSFETs (Q3') are all connected in common, a word line (W12) to which gate electrodes of said MNOS transistors (Q2') are connected in common, and a MOSFET (Q4') which short-circuits said common source line (CS) and said word line (W12) in a reading operation. (Fig. 4)
References Cited (Backward Citations)
No citation records indexed.
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